TMPR4955AF datasheet(156/168 Pages) TOSHIBA

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Chapter 9 Debug Support Unit

9-4

9.9

Debug Exception

Three kinds of debug exception are supported.

• Debug Single Step (DSS bit)

• Debug Breakpoint Exception (SDBBP Instruction)

• JTAG Break Exception (Jtagbrk bit in JTAG_Control_Register)

Note: During real time debugging, first two functions are disabled.

9.9.1

Debug Single Step (DSS)

When the debug register DSS bit is set, this exception has been raised each time one

instruction is executed.

9.9.2

Debug Breakpoint exception (Dbp)

This exception is raised when SDBBP instruction is executed.

9.9.3

JTAG Break Exception

This exception is raised when JTAG unit set the Jtagbrk in JTAG_Control_Register.

9.9.4

Debug Exception Handling

Updates DEPC and Debug register.

Registers other than DEPC and Debug register retain their values.

9.9.5

Branching to debug handler

If the ProbEnb bit in JTAG_Control_Register[15] is set, the debug exception vector is

located at

PC: 0xffff ffff ff20 0200

If the ProbEnb bit in JTAG_Conctrol_Register[15] is cleared, the debug exception vector

is located at

PC: 0xffff ffff bfc0 0400

9.9.6

Exception handling when in Debug Mode (DM bit is set)

All interrupts including NMI are masked. When the NMI interrupt has occurred during

Debug mode, it is stored internally and the NMI interrupt is taken after debug handler is

finished (DM is clear)

9.10 Real Time PC TRACE Output

In real time mode non-sequential Program Counter and trace information are outputted on

TPC[3:0] and PCST[8:0] at 1/3 of the processor clock speed.

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