TMPR4955AF datasheet(142/168 Pages) TOSHIBA

142 / 168 page

Chapter 7 JTAG Interface

7-8

•

Test-Logic-Reset

When the TAP controller is in the Reset state, the value 0x3 is loaded into the

parallel output latch, selecting the Device Identification register as default. The

three most significant bits of the Boundary-scan register are cleared to 0, disabling

the outputs.

The controller remains in this state while JTMS is high. If JTMS is held low while

the controller is in this state, then the controller moves to the Run-Test/Idle state.

•

Run-Test/Idle

In the Run-Test/Idle state, the IC is put in a test mode only when certain

instructions such as a built-in self test (BIST) instruction are present. For

instructions that do not cause any activities in this state, all test data registers

selected by the current instruction retain their previous states.

The controller remains in this state while JTMS is held low. When JTMS is high,

the controller moves to the Select-DR-Scan state.

•

Select-DR-Scan

This is a temporary controller state. Here, the IC does not execute any specific

functions.

If JTMS is held low when the controller is in this state, then the controller moves

to the Capture-DR state. If JTMS is held high, the controller moves to the

Select-IR-Scan state in the instruction column.

•

Select-IR-Scan

This is a temporary controller state. Here, the IC does not execute any specific

functions.

If JTMS is held low when the controller is in this state, then the controller moves

to the Capture-IR state. If JTMS is held high, the controller returns to the

Test-Logic-Reset state.

•

Capture-DR

In this controller state, if the test data register selected by the current instruction

on the rising edge of JTCK has parallel inputs, then data can be parallel-loaded

into the shift portion of the data register. If the test data register does not have

parallel inputs, or if data need not be loaded into the selected data register, then

the data register retains its previous state.

If JTMS is held low while the controller is in this state, the controller moves to the

Shift-DR state. If JTMS is held high, the controller moves to the Exit1-DR state.

•

Shift-DR

In this controller state, the test data register connected between JTDI and JTDO

shifts data one stage forward towards its serial output.

When the controller is in this state, then it remains in the Shift-DR state if JTMS

is held low, or moves to the Exit1-DR state if JTMS is held high.

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