TMPR4955AF datasheet(145/168 Pages) TOSHIBA

145 / 168 page

Chapter 7 JTAG Interface

7-11

7.4

Instructions for JTAG

This section defines the instructions supplied and the operations that occur in response to

those instructions.

7.4.1

The EXTEST Instruction

This instruction is used for external interconnect test, and targets the boundary scan

pins to shift out test patterns in the Update-DR state and those at input pins to capture

test results in the Capture-DR state.

Typically, before EXTEST is executed, the initialization pattern is first shifted into the

boundary scan register using the SAMPLE/PRELOAD instruction. In the Update-DR state,

the boundary scan register loaded with the initialization pattern causes known data to be

driven immediately from the IC onto its external interconnects. This eliminates the

possibility that bus conflicts damage the IC outputs. The flow of data through the boundary

scan register while the EXTEST instruction is selected is shown in Figure 7.4.1, which

follows:

Figure 7.4.1 Test Data Flow While the EXTEST Instruction is Selected

The following steps describe the basic test algorithm of an external interconnect test.

1. Initialize the TAP controller to the Test-Logic-Reset state.

2. Load the instruction register with SAMPLE/PRELOAD. This causes the boundary

scan register to be connected between JTDI and JTDO.

3. Initialize the boundary scan register by shifting in determinate data.

4. Then, load the initial test data into the boundary scan register.

5. Load the instruction register with EXTEST.

6. Capture the data applied to the input pin into the boundary scan register.

7. Shift out the captured data while simultaneously shifting in the next test pattern.

8. Read out the data in the boundary scan register onto the output pin.

Steps 6 to 8 are repeated for each test pattern.

Core Logic

OUTPUT

JTDO

INPUT

JTDI

Boundary Scan Path

TMPR4955AF датащи(PDF) 145 Page - Toshiba Semiconductor