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TMPR4955AF датащи(PDF) 129 Page - Toshiba Semiconductor

номер детали TMPR4955AF
подробное описание детали  64-Bit TX System RISC TX49 Family
PDF  168 Pages
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производитель  TOSHIBA [Toshiba Semiconductor]
домашняя страница  http://www.semicon.toshiba.co.jp/eng
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TMPR4955AF датащи(HTML) 129 Page - Toshiba Semiconductor

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Chapter 6 TX4955A System Interface
6-57
EOD
Data
Hi-Z
Hi-Z
Hi-Z
Addr
Read
8
611
10
9
7
5
4
3
2
1
SysAD(31:0)
SCycle
SClock
SysCmd(4:0)
EValid*
PValid*
EOK*
EReq*
PMaster*
12
Data
Addr
Hi-Z
Hi-Z
Hi-Z
Figure 6.3.31 Discarding and Re-executing Processor Single Read Request
6.3.17
Multiple Drivers on the SysAD Bus
In most applications, the SysAD bus is a point-to-point connection between the processor
and a bidirectional, registered transceiver located in an external agent. In this application,
the SysAD bus has two possible drivers: the processor and the external agent.
However, an application may add additional drivers and receivers to the SysAD bus,
allowing transmissions over the SysAD bus that bypass the processor. To accomplish this,
the external agent(s) must coordinate its use of the SysAD bus by using arbitration
handshake signals such as EReq
EReq
EReq
EReq* and PMaster
PMaster
PMaster
PMaster*.
To implement an independent transmission on the SysAD bus that does not involve the
processor, the system executes the following sequence of actions:
1. The external agent(s) requests the SysAD bus by asserting EReq
EReq
EReq
EReq*.
2. The processor releases the System interface to slave state.
3. The external agent(s) allows independent transmission over the SysAD bus,
making certain the EValid
EValid
EValid
EValid* input to the processor is not asserted while the
transmission occurs.
4. When the transmission is complete, the external agent(s) deasserts EReq
EReq
EReq
EReq* to
return the system interface to master state.
To implement multiple drivers, separate Valid
Valid
Valid
Valid lines are required for non-processor chips
to communicate.



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