TMPR4955AF datasheet(128/168 Pages) TOSHIBA

128 / 168 page

Chapter 6 TX4955A System Interface

6-56

6.3.15

Starvation and Deadlock Avoidance.

Careful use of the EReq

EReq

EReq* signal allows a system to avoid starvation and deadlock

situations.

Whenever an external agent needs the bus, it can request the bus by asserting EReq

EReq

EReq*.

The external agent is guaranteed to gain mastership of the bus after accepting at most one

read/write request from the processor. If the external agent also deasserts EOK

EOK

EOK*, it is

guaranteed to gain mastership of the bus without accepting any read/write request from

the processor.

The external agent can allow the processor to gain bus mastership, perform one

read/write request and then relinquish mastership by the following sequence of actions:

deassert EReq

EReq

EReq*

assert EReq

EReq

EReq*

arbitrate for the bus while asserting EOK

EOK

EOK*

The minimum deassertion of EReq

EReq

EReq* can be one cycle in length.

shows an external agent relinquishing the bus to allow a single read/write request from

the processor. The external agent must be ready to accept this request by keeping EOK

EOK

EOK*

asserted, otherwise the read/write request is held off or killed and the processor

relinquishes bus mastership without extending a request. This could lead to starvation of

the processor.

EOD

Data

Data 0 Data 1

Write

Addr

611

SysAD

SCycle

SClock

SysCmd

PValid*

EOK*

EReq*

PMaster*

Figure 6.3.30 External Agent Gives Up Bus for One Processor Request

6.3.16

Discarding and Re-Executing Read Command

Figure 6.3.31 illustrates how a processor single read request is discarded and reexecuted.

The following sequence describes the protocol.

•

Because the EOK

EOK

EOK* signal is low in cycle 5, the processor tries to issue an address

(cycle 6).

•

If the EOK

EOK

EOK* signal is high at this point, the processor discards this read request

and enters the slave status in the next cycle.

•

Because the EReq

EReq

EReq* signal is inactive, the processor returns to the master status

again and reissues a read request. Because the EOK

EOK

EOK* signal is low in both the

cycles 7 and 8, the issuance cycle of the read request is determined.

•

The external agent outputs data at the requsted address.

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