TMPR4955AF datasheet(111/168 Pages) TOSHIBA

111 / 168 page

Chapter 6 TX4955A System Interface

6-39

6.3.4.3

External Arbitration

The System interface must be in slave state for the external agent to issue an

external request through the System interface. The transition from master state to

slave state is arbitrated by the processor using the System interface handshake

signals EReq

EReq

EReq* and PMaster

PMaster

PMaster*. This transition is described by the following procedure:

1. An external agent signals that it wishes to issue an external request by asserting

EReq

EReq*.

2. When the processor is ready to accept an external request, it releases the System

interface from master to slave state by negating PMaster

PMaster

PMaster*.

3. The System interface returns to master state as soon as the issue of the external

request is complete.

6.3.4.4

Uncompelled Change to Slave State

uncompelled change to slave state is the transition of the System interface from

master state to slave state, initiated by the processor itself when a processor read

request is pending. PMaster

PMaster

PMaster* is negated automatically after a read request. An

uncompelled change to slave state occurs either during or some number of cycles after

the issue cycle of a read request.

The uncompelled release latency depends on the state of the cache. After an

uncompelled change to slave state, the processor returns to master state at the end of

the next external request. This can be a read response, or some other type of external

request.

An external agent must note that the processor has performed an uncompelled

change to slave state and begin driving the SysAD

SysAD

SysAD bus along with the SysCmd

SysCmd

SysCmd bus. As

long as the System interface is in slave state, the external agent can begin an external

request without arbitrating for the System interface; that is, without asserting EReq

EReq

EReq*.

After the external request, the System interface returns to master state.

6.3.4.5

Signal Timing

The System interface protocol describes the cycle-by-cycle signal transitions that

occur on the pins of the system interface to realize requests between the processor and

an external agent. Figure 6.3.3 shows the timing relationships between System

interface signal edges.

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