TMPR4955AF datasheet(108/168 Pages) TOSHIBA

108 / 168 page

Chapter 6 TX4955A System Interface

6-36

6.3.3.2

Load Miss

When the processor misses in the data cache on a load, it obtains a cache line of data

from an external agent. The processor issues a read request for the cache line and

waits for an external agent to provide the data in response to this read request. If the

cache data which the incoming line will replace contains valid dirty data, this data is

written to memory. The read completes before the write of the dirty cast-out data.

6.3.3.3

Store Miss

When the processor misses in the data cache on a store, it issues a read request to

bring a cache line of data into the cache, where it is then updated with the store data. If

the cache data which the incoming line will replace contains valid dirty data, the data

is written to memory. The read completes before the write of the dirty cast-out data.

To guarantee that cached data written by a store is consistent with main memory,

the corresponding cache line must be explicitly flushed from the cache using a cache

operation.

6.3.3.4

Uncached Load or Store

When the processor performs an uncached load, it issues a read request and waits

for a single transfer of read response data from an external agent.

When the processor performs an uncached store, it issues a write request and

provides a single transfer of data to the external agent.

The processor does not consolidate data on uncached writes. For example, writes of

two contiguous halfwords takes two write cycles, they are never grouped into a single

word write.

6.3.3.5

Cache Instructions

The TX4955A processor provides a number of cache instructions for use in

maintaining the state and contents of the caches. Cache operations supported in the

TX4955A processor are described in Chapter 5.

6.3.3.6

Byte Ordering (Endian)

The System interface byte order is set by the Endian

Endian

Endian of external pin. The byte order

is big-endian when Endian

Endian

Endian is high, and little-endian when Endian

Endian

Endian is low. The

(reverse-endian) bit in the

Status register can be set by software to reverse the byte

order available in User mode.

6.3.3.7

Physical Addresses

Physical addresses are driven on SysAD (31:0)

SysAD (31:0)

SysAD (31:0) during address cycles.

6.3.3.8

Interface Buses

Figure 6.3.1 shows the primary communication paths for the System interface: a

32-bit address and data bus, SysAD (31:0)

SysAD (31:0)

SysAD (31:0), and a 5-bit command bus, SysCmd (4:0)

SysCmd (4:0)

SysCmd (4:0).

These SysAD

SysAD

SysAD and the SysCmd

SysCmd

SysCmd buses are bidirectional; that is, they are driven by the

processor to issue a processor request, and by the external agent to issue an external

request.

A request through the System interface consists of:

•

an address

•

a System interface command that specifies the precise nature of the request

•

a series of data elements if the request is for a write or read response.

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