TMPR4955AF datasheet(110/168 Pages) TOSHIBA

110 / 168 page

Chapter 6 TX4955A System Interface

6-38

6.3.4

System Interface Protocols

Figure 6.3.2 shows the register-to-register operation of the System interface. That is,

processor outputs come directly from output registers and begin to change with the rising

edge of SClock

SClock

SClock.†

Processor inputs are fed directly to input registers that latch these input signals with the

rising edge of SClock

SClock

SClock. This allows the System interface to run at the highest possible clock

frequency.

TX4955A

SClock

Input data

Output data

Figure 6.3.2 System Interface Register-to-Register Operation

6.3.4.1

Master and Slave States

When the TX4955A processor is driving the SysAD

SysAD

SysAD and SysCmd

SysCmd

SysCmd buses, the System

interface is in

master state. When the external agent is driving the SysAD

SysAD

SysAD and

SysCmd

SysCmd buses, the System interface is in

slave state.

In master state, the processor asserts the signal PValid

PValid

PValid* whenever the SysAD

SysAD

SysAD and

SysCmd

SysCmd buses are valid.

In slave state, the external agent asserts the signal EValid

EValid

EValid* whenever the SysAD

SysAD

and SysCmd

SysCmd

SysCmd buses are valid.

6.3.4.2

Moving from Master to Slave State

The processor is the default master of the system interface. An external agent

becomes master of the system interface through arbitration, or by default after a

processor read request. The external agent returns mastership to the processor after

an external request completes.

The System interface remains in master state unless one of the following occurs:

•

The external agent requests and is granted the System interface (external

arbitration).

•

The processor issues a read request (uncompelled change to slave state).

The following sections describe these two actions.

† SClock

SClock

SClock is an internal clock used by the processor to sample data at the System interface and to clock data into

the processor System interface output registers.

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