HC705C9AGRSSLASHD datasheet(142/157 Pages) NXP

142 / 157 page

General Release Speciﬁcation

Serial Peripheral Interface Timing

MC68HC705C9A — Rev. 2.0

Electrical Specifications

Table 12-6. Serial Peripheral Interface Timing (V

DD = 3.3 Vdc)*

Num

Characteristic

Symbol

Min

Max

Unit

Operating Frequency

Master

Slave

(M)

(S)

0.5

1.0

MHz

Cycle Time

Master

Slave

CYC

(M)

CYC

(S)

2.0

1.0

—

CYC

µs

Enable Lead Time

Master

Slave

LEAD

(M)

LEAD

(S)

†

500

—

Enable Lag Time

Master

Slave

LAG

(M)

LAG

(S)

†

1.5

—

µs

Clock (SCK) High Time

Master

Slave

(SCKH)M

(SCKH)S

720

400

—

Clock (SCK) Low Time

Master

Slave

(SCKL)M

(SCKL)S

720

400

—

Data Setup Time (Inputs)

Master

Slave

(M)

(S)

200

—

Data Hold Time (Inputs)

Master

Slave

(M)

(S)

200

—

Slave Access Time (Time to Data Active from

High-Impedance State)

250

Slave Disable Time (Hold Time to High-Impedance State)

DIS

—

500

Data Valid

Master (Before Capture Edge)

Slave (After Enable Edge)‡

(M)

(S)

0.25

—

500

CYC

(M)

Data Hold Time (Outputs)

Master (After Capture Edge)

Slave (After Enable Edge)

(M)

(S)

0.25

—

CYC

(M)

Rise Time (20% V

DD to 70% VDD, CL = 200 pF)

SPI Outputs (SCK, MOSI, and MISO)

SPI Inputs (SCK, MOSI, MISO, and SS)

—

200

2.0

µs

Fall Time (70% V

DD to 20% VDD, CL = 200 pF)

SPI Outputs (SCK, MOSI, and MISO)

SPI Inputs (SCK, MOSI, MISO, and SS)

—

200

2.0

µs

NOTES:

* V

DD = 3.3 Vdc ± 0.3 Vdc; VSS = 0 Vdc, TA = –40 to +85 °C. Refer to Figure 12-7 and Figure 12-8 for timing diagrams.

† Signal production depends on software

‡ Assumes 200 pF load on all SPI pins.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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