HC705C9AGRSSLASHD datasheet(137/157 Pages) NXP

137 / 157 page

General Release Specification

Control Timing

MC68HC705C9A — Rev. 2.0

Electrical Specifications

12.7 Control Timing

Table 12-3. Control Timing (VDD = 5.0 V ±10%)

(1)

Characteristic

Symbol

Min

Max

Unit

Frequency of Operation

Crystal

External Clock

fOSC

—

4.2

MHz

Internal Operating Frequency (fOSC ÷ 2)

Crystal

External Clock

fOP

—

2.1

MHz

Cycle Time

tCYC

480

—

Crystal Oscillator Startup Time

tOXOV

—

100

Stop Recovery Start-up Time (Crystal Oscillator)

tILCH

—

100

RESET Pulse Width

tRL

1.5

—

tCYC

Timer

Resolution(2)

Input Capture Pulse Width

Input Capture Pulse Period

tRESL

tTH, tTL

tTLTL

4.0

125

(3)

—

tCYC

Interrupt Pulse Width Low (Edge-Triggered)

tILIH

125

—

Interrupt Pulse Period

tILIL

(4)

—tCYC

OSC1 Pulse Width

tOH,tOL

—

NOTES:

1. V

DD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 to +85 °C, unless otherwise noted

2. Because a 2-bit prescaler in the timer must count four internal cycles (t

CYC), this is the limiting

minimum factor in determining the timer resolution.

3. The minimum period t

TLTL should not be less than the number of cycle times it takes to execute the

capture interrupt service routine plus 24 t

CYC.

4. The minimum t

ILIL should not be less than the number of cycle times it takes to execute the

interrupt service routine plus 19 t

CYC.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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