CS47L35 datasheet(197/300 Pages) CIRRUS

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DS1085F3

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CS47L35

4.16 Clocking and Sample Rates

Figure 4-65. FLL Configuration

The procedure for configuring the FLL is described in the following subsections. Note that the configuration of the main

FLL path and the FLL synchronizer path are very similar. One or both paths must be configured, depending on the

application requirements:

• If a single clock input reference is used, only the main FLL path should be used.

• If the input reference to the main FLL is intermittent, or may be interrupted unexpectedly, only the main FLL path

should be used.

• If two clock input references are used, the constant or low-noise clock is configured on the main FLL path and the

high-accuracy clock is configured on the FLL synchronizer path. Note that the synchronizer input must be

synchronous with the audio data.

4.16.9.3 Input Frequency Control

The main input reference is selected using FLL1_REFCLK_SRC. The synchronizer input reference is selected using

FLL1_SYNCCLK_SRC. The available options in each case are MCLK1, MCLK2, SLIMCLK, AIFnBCLK, or AIFnLRCLK.

The SLIMCLK reference is controlled by an adaptive divider on the external SLIMCLK input. The divider automatically

adapts to the SLIMbus clock gear, to provide a constant reference frequency for the FLL—see Section 4.10.7.

The FLL1_REFCLK_DIV field controls a programmable divider on the main input reference. The FLL1_SYNCCLK_DIV

field controls a programmable divider on the synchronizer input reference. Each input can be divided by 1, 2, 4 or 8. The

divider should be set to bring each reference down to 13.5 MHz or below. For best performance, it is recommended that

the highest possible frequency—within the 13.5 MHz limit—should be selected.

4.16.9.4 Output Frequency Control—Main Loop

The FLL output frequency, relative to the main input reference FREF, is a function of the following:

• The FLL oscillator frequency, FVCO

• The frequency ratio set by FLL1_FRATIO

• The real number represented by N.K. (N = integer; K = fractional portion)

The FVCO frequency must be in the range 270–300 MHz.

MCLK2

MCLK1

FLL1_REFCLK_SRC

FVCO (270MHz ≤ Fvco ≤ 300MHz)

FOUT (SYSCLK)

Divide by 3

FLL1_ENA (FLL Enable)

AIFnBCLK,

AIFnLRCLK

Divide by 1, 2, 4 or 8

Divide by

FLL1_REFCLK_DIV

REF <

13.5MHz

FREF

Multiply

by N.K

Multiply by

FLL1_FRATIO

Multiply by

1, 2, 3 … 16

Main FLL path

FLL1_SYNCCLK_SRC

SLIMCLK

SLIMCLK_REF_GEAR

Divide by

FLL1_SYNCCLK_DIV

Divide by 1, 2, 4 or 8

FSYNC <

13.5MHz

FSYNC

Multiply

by N.K

(Sync )

Multiply by

FLL1_SYNC_F

RATIO

Multiply by

1, 2, 4, 8 or 16

FLL Synchronizer path

FOUT (GPIO)

Divide by 7, 8 … 127

Divide by

FLL1_GPCLK_DIV

Divide by 2

FOUT (DSPCLK)

FLL1_SYNC_ENA

(FLL Synchronizer Enable)

Automatic

Divider

Synchronizer disabled:

Synchronizer enabled:

N.K (Sync) = FLL1_SYNC_N +

FLL1_SYNC_THETA

FLL1_SYNC_LAMBDA

N.K = FLL1_N +

FLL1_THETA

65536

N.K = FLL1_N +

FLL1_THETA

FLL1_LAMBDA

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