CS47L35 datasheet(199/300 Pages) CIRRUS

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DS1085F3

199

CS47L35

4.16 Clocking and Sample Rates

Other FLL fields are configured as follows:

• FLL1_PHASE_GAIN must be set to 0x2 in all cases.

• FLL1_CTRL_RATE must be set to 0x1 in all cases.

4.16.9.5 Output Frequency Control—Synchronizer Loop

A similar procedure applies for the derivation of the FLL synchronizer parameters—assuming that this function is used.

The FLL1_SYNC_FRATIO field selects the frequency division ratio of the FLL synchronizer input. The FLL1_GAIN and

FLL1_SYNC_DFSAT fields are used to optimize the FLL, according to the input frequency. These fields should be set as

described in Table 4-95.

Note: The FLL1_SYNC_FRATIO coding differs from that of FLL1_FRATIO.

The FLL oscillator frequency, FVCO, is the same frequency calculated as described in Section 4.16.9.4.

The value of N.KSYNC can then be determined as follows:

N.KSYNC =FVCO / (FLL1_SYNC_FRATIO x 3 x FSYNC)

Note that, in the above equation, the following interpretations are assumed:

•FSYNC is the synchronizer input frequency, after division by FLL1_SYNCCLK_DIV, where applicable

• FLL1_SYNC_FRATIO is the FVCO clock ratio (1, 2, 4, 8, or 16)

The value of NSYNC is held in FLL1_SYNC_N.

The value of KSYNC is determined by the FLL1_SYNC_THETA and FLL1_SYNC_LAMBDA fields:

• In Integer Mode (KSYNC = 0), FLL1_SYNC_THETA must be set to 0. The FLL1_SYNC_THETA field is not used in

Integer Mode.

• In Fractional Mode (KSYNC > 0), the FLL1_SYNC_THETA and FLL1_SYNC_LAMBDA fields can be derived as

described in Section 4.16.9.6.

The FLL1_SYNC_N, FLL1_SYNC_THETA, and FLL1_SYNC_LAMBDA fields are all coded as integers (LSB = 1).

4.16.9.6 Calculation of Theta and Lambda

In Fractional Mode, with the synchronizer disabled (K > 0, and FLL1_SYNC_ENA = 0), FLL1_THETA and FLL1_LAMBDA

are calculated with the following steps:

1. Calculate GCD(FLL) using the Greatest Common Denominator function:

GCD(FLL) = GCD(FLL1_FRATIO x FREF, FVCO /3),

where GCD(x, y) is the greatest common denominator of x and y.

FREF is the input frequency, after division by FLL1_REFCLK_DIV, where applicable.

2. Calculate FLL1_THETA and FLL1_LAMBDA using the following equations:

FLL1_THETA = ((FVCO / 3) – (FLL1_N x FLL1_FRATIO x FREF)) / GCD(FLL)

FLL1_LAMBDA = (FLL1_FRATIO x FREF)/ GCD(FLL)

Table 4-95. Selection of FLL1_SYNC_FRATIO, FLL1_SYNC_GAIN, FLL1_SYNC_DFSAT

Condition

FLL1_SYNC_FRATIO

FLL1_SYNC_GAIN

FLL1_SYNC_DFSAT

1MHz

 FSYNC < 13.5 MHz

0x0 (divide by 1)

0x4 (16x gain)

0 (wide bandwidth)

256 kHz

 FSYNC < 1 MHz

0x1 (divide by 2)

0x2 (4x gain)

0 (wide bandwidth)

128 kHz

 FSYNC < 256 kHz

0x2 (divide by 4)

0x0 (1x gain)

0 (wide bandwidth)

64 kHz

 FSYNC < 128 kHz

0x3 (divide by 8)

0x0 (1x gain)

1 (narrow bandwidth)

FSYNC < 64 kHz

0x4 (divide by 16)

0x0 (1x gain)

1 (narrow bandwidth)

Note: FSYNC is the synchronizer input frequency, after division by FLL1_SYNCCLK_DIV, where applicable.

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