CS47L35 datasheet(200/300 Pages) CIRRUS

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DS1085F3

CS47L35

4.16 Clocking and Sample Rates

Note also that the values of FLL1_THETA and FLL1_LAMBDA must be coprime (i.e., not divisible by any common integer).

The value of K must be less than 1 (i.e., FLL1_THETA must be less than FLL1_LAMBDA).

If the synchronizer is enabled, the FLL1_SYNC_THETA and FLL1_SYNC_LAMBDA fields are calculated in the same

manner described above, using the corresponding synchronizer parameters.

In Fractional Mode, with the synchronizer enabled (K > 0, and FLL1_SYNC_ENA = 1), FLL1_THETA is calculated as

FLL1_THETA = K x 65536. The FLL1_LAMBDA field is ignored in this case, and the coprime requirement for FLL1_

LAMBDA and FLL1_THETA is not applicable.

4.16.9.7 Free-Running FLL Mode

The FLL can generate a clock signal even if no external reference is available. This may be because the normal input

reference has been interrupted, or may be during a standby or start-up period when no initial reference clock is available.

Free-Running FLL Mode is enabled by setting FLL1_FREERUN. Note that FLL1_ENA must also be enabled in

Free-Running FLL Mode.

In Free-Running FLL Mode, the normal feedback mechanism of the FLL is halted and the FLL oscillates independently of

the external input references.

If the FLL was previously operating normally (with an input reference clock), the FLL output frequency remains unchanged

when Free-Running FLL Mode is enabled. The FLL output is independent of the input reference while operating with

FLL1_FREERUN = 1.

The main FLL loop always runs freely if the input reference clock is stopped (regardless of the FLL1_FREERUN setting).

If FLL1_FREERUN = 0, the FLL relocks to the input reference whenever it is available.

In Free-Running FLL Mode, (with FLL1_FREERUN = 1), the FLL integrator value (part of the feedback mechanism) can

be commanded directly using FLL1_FRC_INTEG_VAL. The integrator value in this field is applied to the FLL when a 1 is

written to FLL1_FRC_INTEG_UPD.

If the FLL is started up in Free-Running FLL Mode, (i.e., it was not previously running), the default value of FLL1_FRC_

INTEG_VAL is applied.

The FLL integrator value (part of the feedback mechanism) can be read from the FLL1_INTEG field; the value of this field

may be stored for later use. Note that the value of FLL1_INTEG is only valid if FLL1_FREERUN = 1 and the FLL1_INTEG_

VALID = 1.

The FLL integrator setting does not ensure a specific output frequency for the FLL across all devices and operating

conditions; some level of variation applies.

The free-running FLL clock may be selected as the SYSCLK or DSPCLK source, as shown in Fig. 4-63.

4.16.9.8 Spread-Spectrum FLL Control

The CS47L35 can apply modulation to the FLL output, using spread-spectrum techniques. This can be used to control the

EMI characteristics of the circuits that are clocked via the FLL.

The FLL can be configured for triangle modulation, zero mean frequency modulation (ZMFM), or dither. The amplitude

and frequency parameters of the spread spectrum functions is also programmable, using the fields described in

Section 4.16.9.9.

4.16.9.9 FLL Control Registers

The FLL control registers are described in Table 4-96.

Example settings for a variety of reference frequencies and output frequencies are shown in Section 4.16.9.12.

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