MPC8560CPX667JC datasheet(102/108 Pages) NXP

102 / 108 page

MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2

102

Freescale Semiconductor

Document Revision History

2.0

Section 1.1—Updated features list to coincide with latest version of the reference manual

Table 1 and Table 2— Addition of CPM to OVDD and OVIN; Addition of SYSCLK to OVIN

Table 2—Addition of notes 1 and 2

Table 3—Addition of note 1

Table 5—New

Section 4—New

Table 13—Addition of IVREF

Table 15—Modified maximum values for tDISKEW

Table 16—Added MSYNC_OUT to tMCKSKEW2

Figure 5—New

Section 6.2.1—Removed Figure 4, "DDR SDRAM Input Timing Diagram"

Section 7.1—Removed references to 2.5 V from first paragraph

Figure 8—New

Table 19 and Table 20—Modified “conditions” for IIH and I IL

Table 21—Addition of min and max for GTX_CLK125 reference clock duty cycle

Table 25—Addition of min and max for GTX_CLK125 reference clock duty cycle

Table 27—Addition of min and max for GTX_CLK125 reference clock duty cycle

Figure 17 and Figure 19—Changed LSYNC_IN to Internal clock at top of each figure

Table 34—Modified values for tFIIVKH, tNIIVKH, and tTDIVKH; addition of tPIIVKH and tPIIXKH.

Table 35—Modified values for tFEKHOX, tNIKHOX,tNEKHOX, tTDKHOX; addition of tPIKHOX.

Figure 16—New

Figure 30—New

Figure 16—New

Table 31—Removed row for tLBKHOX3

Table 44—New (AC timing of PCI-X at 66 MHz)

Table 54—Addition of note 19

Figure 61—Addition of jumper and note at top of diagram

Table 56—Changed max bus freq for 667 core to 166

Section 16.2.1—Modified first paragraph

Figure 52—Modified

Figure 53—New

Table 60—Modified thermal resistance data

Section 16.2.4.2—Modified first and second paragraphs

Table 62. Document Revision History (continued)

Rev. No.

Substantive Change(s)

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