MPC8560CPX667JC datasheet(45/108 Pages) NXP

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MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2

Freescale Semiconductor

CPM

Figure 16 provides the AC test load for the CPM.

Figure 23. CPM AC Test Load

Figure 24 through Figure 29 represent the AC timing from Table 34 and Table 35. Note that although the

specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when

the falling edge is the active edge.

COL/CRS width high (FCC)

tFCCH

1.5

CLK

Notes:

1.Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of

Serial Clock. Timings are measured at the pin.

2.The symbols used for timing specifications herein follow the pattern of t(first two letters of functional

block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for

outputs. For example, tFIIVKH symbolizes the FCC inputs internal timing (FI) with respect to the time the

input signals (I) reaching the valid state (V) relative to the reference clock tFCC (K) going to the high (H)

state or setup time. And tTDIXKH symbolizes the TDM timing (TD) with respect to the time the input

signals (I) reach the invalid state (X) relative to the reference clock tFCC (K) going to the high (H) state

or hold time.

3.PIO and TIMER inputs and outputs are asynchronous to SYSCLK or any other externally visible clock.

PIO/TIMER inputs are internally synchronized to the CPM internal clock. PIO/TIMER outputs should be

treated as asynchronous.

Table 35. CPM Output AC Timing Specifications 1

Characteristic

Symbol 2

Min

Max

Unit

FCC outputs—internal clock (NMSI) delay

tFIKHOX

15.5

FCC outputs—external clock (NMSI) delay

tFEKHOX

SCC/SPI outputs—internal clock (NMSI) delay

tNIKHOX

0.5

SCC outputs—external clock (NMSI) delay

tNEKHOX

SPI output—external clock (NMSI) delay

tSEKHOX

211

TDM outputs/SI delay

tTDKHOX

2.5

Notes:

1.Output specifications are measured from the 50% level of the rising edge of Serial Clock to the 50% level of the

signal. Timings are measured at the pin.

2.The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)

(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,

tFIKHOX symbolizes the FCC inputs internal timing (FI) for the time tFCC memory clock reference (K) goes from the

high state (H) until outputs (O) are invalid (X).

Table 34. CPM Input AC Timing Specifications 1 (continued)

Characteristic

Symbol 2

Min 3

Unit

Output

OVDD/2

RL = 50 Ω

Z0 = 50 Ω

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