MPC8560CPX667JC datasheet(35/108 Pages) NXP

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MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2

Freescale Semiconductor

Local Bus

Input setup to local bus clock (except

LUPWAIT)

—tLBIVKH1

1.8

—

4, 5, 8

LUPWAIT input setup to local bus clock

—

tLBIVKH2

1.7

—

4, 5

Input hold from local bus clock (except

LUPWAIT)

—tLBIXKH1

0.5

—

4, 5, 8

LUPWAIT input hold from local bus clock

—

tLBIXKH2

1.0

—

4, 5

LALE output transition to LAD/LDP output

transition (LATCH hold time)

—tLBOTOT

1.5

—

Local bus clock to output valid (except

LAD/LDP and LALE)

TSEC2_TXD[6:5] = 00

tLBKHOV1

—

2.0

4, 8

TSEC2_TXD[6:5] = 11

(default)

3.5

Local bus clock to data valid for LAD/LDP

TSEC2_TXD[6:5] = 00

tLBKHOV2

—

2.2

4, 8

TSEC2_TXD[6:5] = 11

(default)

3.7

Local bus clock to address valid for LAD

TSEC2_TXD[6:5] = 00

tLBKHOV3

—

2.3

4, 8

TSEC2_TXD[6:5] = 11

(default)

3.8

Local bus clock to LALE assertion

tLBKHOV4

—

2.3

4, 8

Output hold from local bus clock (except

LAD/LDP and LALE)

TSEC2_TXD[6:5] = 00

tLBKHOX1

0.7

—

4, 8

TSEC2_TXD[6:5] = 11

(default)

1.6

Output hold from local bus clock for

LAD/LDP

TSEC2_TXD[6:5] = 00

tLBKHOX2

0.7

—

4, 8

TSEC2_TXD[6:5] = 11

(default)

1.6

Local bus clock to output high Impedance

(except LAD/LDP and LALE)

TSEC2_TXD[6:5] = 00

tLBKHOZ1

—

2.5

7, 9

TSEC2_TXD[6:5] = 11

(default)

3.8

Table 31. Local Bus General Timing Parameters—DLL Enabled (continued)

Parameter

POR Configuration

Symbol 1

Min

Max

Unit

Notes

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