MPC8560CPX667JC datasheet(9/108 Pages) NXP

9 / 108 page

MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2

Freescale Semiconductor

Electrical Characteristics

2.1.2 Power Sequencing

The MPC8560 requires its power rails to be applied in a specific sequence in order to ensure proper device

operation. These requirements are as follows for power up:

1. VDD, AVDD

2. GVDD, LVDD, OVDD (I/O supplies)

Items on the same line have no ordering requirement with respect to one another. Items on separate lines

must be ordered sequentially such that voltage rails on a previous step must reach 90 percent of their value

before the voltage rails on the current step reach 10 percent of theirs.

DDR DRAM I/O voltage

GVDD

–0.3 to 3.63

—

Three-speed Ethernet I/O voltage

LVDD

–0.3 to 3.63

–0.3 to 2.75

V—

CPM, PCI/PCI-X, local bus, RapidIO, 10/100 Ethernet,MII

management, DUART, system control and power management,

I2C, and JTAG I/O voltage

OVDD

–0.3 to 3.63

Input voltage

DDR DRAM signals

MVIN

–0.3 to (GVDD + 0.3)

2, 5

DDR DRAM reference

MVREF

–0.3 to (GVDD + 0.3)

2, 5

Three-speed Ethernet signals

LVIN

–0.3 to (LVDD + 0.3)

4, 5

CPM, Local bus, RapidIO, 10/100

Ethernet, SYSCLK, system

control and power management,

I2C, and JTAG signals

OVIN

–0.3 to (OVDD + 0.3)

PCI/PCI-X

OVIN

–0.3 to (OVDD + 0.3)

Storage temperature range

TSTG

–55 to 150

°C

—

Notes:

1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and

functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause

permanent damage to the device.

2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

3. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

4. Caution: LVIN must not exceed LVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

5. (M,L,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.

6. OVIN on the PCI interface may overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as

shown in Figure 3.

Table 1. Absolute Maximum Ratings 1 (continued)

Characteristic

Symbol

Max Value

Unit

Notes

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