MPC8560CPX667JC datasheet(3/108 Pages) NXP

3 / 108 page

MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2

Freescale Semiconductor

Overview

— Executes code from internal ROM or instruction RAM

— 32-bit RISC architecture

— Tuned for communication environments: instruction set supports CRC computation and bit

manipulation.

— Internal timer

— Interfaces with the embedded e500 core processor through a 32-Kbyte dual-port RAM and

virtual DMA channels for each peripheral controller

— Handles serial protocols and virtual DMA.

— Three full-duplex fast serial communications controllers (FCCs) that support the following

protocols:

– ATM protocol through UTOPIA interface (FCC1 and FCC2 only)

– IEEE Std 802.3™/Fast Ethernet

– HDLC

– Totally transparent operation

— Two multi-channel controllers (MCCs) that together can handle up to 256 HDLC/transparent

channels at 64 Kbps each, multiplexed on up to 8 TDM interfaces

— Four full-duplex serial communications controllers (SCCs) that support the following

protocols:

– High level/synchronous data link control (HDLC/SDLC)

– LocalTalk (HDLC-based local area network protocol)

– Universal asynchronous receiver transmitter (UART)

– Synchronous UART (1x clock mode)

– Binary synchronous communication (BISYNC)

– Totally transparent operation

— Serial peripheral interface (SPI) support for master or slave

—I2C bus controller

— Time-slot assigner supports multiplexing of data from any of the SCCs and FCCs onto eight

time-division multiplexed (TDM) interfaces. The time-slot assigner supports the following

TDM formats:

– T1/CEPT lines

–T3/E3

– Pulse code modulation (PCM) highway interface

– ISDN primary rate

– Freescale interchip digital link (IDL)

– General circuit interface (GCI)

— User-defined interfaces

— Eight independent baud rate generators (BRGs)

— Four general-purpose 16-bit timers or two 32-bit timers

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