поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

MPC8560CPX667JC датащи(PDF) 61 Page - NXP Semiconductors

номер детали MPC8560CPX667JC
подробное описание детали  Integrated Processor Hardware Specifications
PDF  108 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  NXP [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo NXP - NXP Semiconductors

MPC8560CPX667JC датащи(HTML) 61 Page - NXP Semiconductors

Back Button MPC8560CPX667JC Datasheet HTML 57Page - NXP Semiconductors MPC8560CPX667JC Datasheet HTML 58Page - NXP Semiconductors MPC8560CPX667JC Datasheet HTML 59Page - NXP Semiconductors MPC8560CPX667JC Datasheet HTML 60Page - NXP Semiconductors MPC8560CPX667JC Datasheet HTML 61Page - NXP Semiconductors MPC8560CPX667JC Datasheet HTML 62Page - NXP Semiconductors MPC8560CPX667JC Datasheet HTML 63Page - NXP Semiconductors MPC8560CPX667JC Datasheet HTML 64Page - NXP Semiconductors MPC8560CPX667JC Datasheet HTML 65Page - NXP Semiconductors Next Button
Zoom Inzoom in Zoom Outzoom out
 61 / 108 page
background image
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
61
RapidIO
The peak differential signal of the transmitter output or receiver input, is A – B volts.
The peak-to-peak differential signal of the transmitter output or receiver input, is 2
× (A – B) volts.
Figure 42. Differential Peak-to-Peak Voltage of Transmitter or Receiver
To illustrate these definitions using numerical values, consider the case where a LVDS transmitter has a
common mode voltage of 1.2 V and each signal has a swing that goes between 1.4 and 1.0 V. Using these
values, the peak-to-peak voltage swing of the signals TD, TD, RD, and RD is 400 mV. The differential
signal ranges between 400 and –400 mV. The peak differential signal is 400 mV, and the peak-to-peak
differential signal is 800 mV.
A timing edge is the zero-crossing of a differential signal. Each skew timing parameter on a parallel bus
is synchronously measured on two signals relative to each other in the same cycle, such as data to data,
data to clock, or clock to clock. A skew timing parameter may be relative to the edge of a signal or to the
middle of two sequential edges.
Static skew represents the timing difference between signals that does not vary over time regardless of
system activity or data pattern. Path length differences are a primary source of static skew.
Dynamic skew represents the amount of timing difference between signals that is dependent on the activity
of other signals and varies over time. Crosstalk between signals is a source of dynamic skew.
Eye diagrams and compliance masks are a useful way to visualize and specify driver and receiver
performance. This technique is used in several serial bus specifications. An example compliance mask is
shown in Figure 43. The key difference in the application of this technique for a parallel bus is that the data
is source synchronous to its bus clock while serial data is referenced to its embedded clock. Eye diagrams
reveal the quality (cleanness, openness, goodness) of a driver output or receiver input. An advantage of
using an eye diagram and a compliance mask is that it allows specifying the quality of a signal without
requiring separate specifications for effects such as rise time, duty cycle distortion, data dependent
dynamic skew, random dynamic skew, etc. This allows the individual semiconductor manufacturer
maximum flexibility to trade off various performance criteria while keeping the system performance
constant.
In using the eye pattern and compliance mask approach, the quality of the signal is specified by the
compliance mask. The mask specifies the maximum permissible magnitude of the signal and the minimum
permissible eye opening. The eye diagram for the signal under test is generated according to the
specification. Compliance is determined by whether the compliance mask can be positioned over the eye
diagram such that the eye pattern falls entirely within the unshaded portion of the mask.
Serial specifications have clock encoded with the data, but the LP-LVDS physical layer defined by
RapidIO is a source synchronous parallel port so additional specifications to include effects that are not
found in serial links are required. Specifications for the effect of bit to bit timing differences caused by
static skew have been added and the eye diagrams specified are measured relative to the associated clock
in order to include clock to data effects. With the transmit output (or receiver input) eye diagram, the user
can determine if the transmitter output (or receiver input) is compliant with an oscilloscope with the
appropriate software.
A V
B V
TD or RD
TD or RD



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com