AD9545 datasheet(3/157 Pages) AD

3 / 157 page

Data Sheet

AD9545

Rev. A | Page 3 of 157

Output Muting.............................................................................52

Distribution Dividers (Q Dividers) ..............................................53

Distribution Dividers Overview ...............................................53

Q Divider Clock Source Selection ............................................53

Integer Division...........................................................................54

Half Integer Division ..................................................................54

Q Divider Reset ...........................................................................54

Q Divider Constraints ................................................................55

Hitless/Zero Delay Feedback.....................................................55

Distribution Phase Offset Control................................................56

Output Phase Offset Overview .................................................56

Initial Phase Offset......................................................................56

Subsequent phase offsets............................................................56

Distribution N-Shot/PRBS Output Clocking ..............................59

N-Shot/PRBS Clocking Overview ............................................59

Randomized clock (PRBS).........................................................60

N-Shot (JESD204B and Gapped Clocking) .............................60

Distribution Embedded Output Clock Modulation...................63

Modulation Controller Overview .............................................63

Modulation Magnitude ..............................................................64

Modulation Period......................................................................64

Balanced and Unbalanced Modulation....................................65

Modulation Sync .........................................................................66

Modulation Trigger.....................................................................67

Distribution Output Clock Synchronization...............................68

Synchronization Overview ........................................................68

Manual Sync Trigger...................................................................68

Autoreconfiguration Sync Trigger ............................................68

Autosync Trigger .........................................................................69

Reference Synchronization ........................................................69

Frequency Translation Loops ........................................................70

Frequency Translation Loops Overview ..................................70

Translation Profiles .....................................................................70

Profile Enable...............................................................................71

Profile Priority .............................................................................71

Input Reference Source Selection .............................................71

Translation Modes.......................................................................71

Phase Buildout Mode..................................................................72

Internal Zero Delay (Hitless) Mode..........................................73

External Zero Delay (Hitless) Mode.........................................74

Source Profiles .................................................................................76

Source Profiles Overview...........................................................76

DPLL Phase/Frequency Lock Detector....................................76

Phase Step Limit..........................................................................76

Skew Adjustment ........................................................................77

Initial Phase Skew Refinement Steps........................................77

Digital PLL (DPLL).........................................................................79

DPLL Overview...........................................................................79

DPLL Loop Controller ...............................................................79

DPLL Feedback Divider (N-Divider).......................................80

DPLL Loop Filter ........................................................................81

DPLL NCO ..................................................................................82

NCO Gain Tuning Word Filter Bandwidth.............................84

DPLL Lock Detectors .................................................................84

Freerun Tuning Word.................................................................86

DPLL Fast Acquisition (FACQ) Options.................................86

DPLL Phase Offset Control .......................................................88

Tuning Word Offset Clamp .......................................................89

Phase Slew Rate Limit ................................................................90

Tuning Word History .................................................................91

Delay Compensation ..................................................................94

Time Stamp Tagging Options....................................................95

Cascaded DPLL Configuration .....................................................97

Caveats of Cascaded DPLL Operation.....................................99

Analog PLL (APLL) ......................................................................100

APLL Overview.........................................................................100

Voltage Controlled Oscillator (VCO).....................................100

APLL Feedback Divider (M-Divider) ....................................101

Phase/Frequency Detector (PFD)...........................................101

Charge Pump.............................................................................101

APLL Loop Filter ......................................................................102

Reference Switching......................................................................103

Reference Switching Overview ...............................................103

Forced Freerun Mode...............................................................104

Forced Holdover Mode ............................................................104

Manual/Automatic Translation Profile Selection .................105

Time to Digital Converter (TDC)...............................................109

Timestamps....................................................................................110

Timestamps Overview .............................................................110

Digital Crosspoint Mux............................................................110

Tagged Time Stamps.................................................................111

User Access to Time Stamps........................................................112

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