AD9545 datasheet(87/157 Pages) AD

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Data Sheet

AD9545

Rev. A | Page 87 of 157

FACQ Bandwidth Control

The FACQ feature is active when the user programs the 4-bit

unsigned Profile x.y fast acquisition excess bandwidth bit field

with a nonzero value. The Profile x.y fast acquisition excess

bandwidth bit fields reside in Bits[3:0] of Register 0x1216,

0x1656, Register 0x1676, Register 0x1696, and Register 0x16B6.

When this value is nonzero, the FACQ controller uses the value

to define the maximum starting loop bandwidth (BW0). The

value in the Profile x.y fast acquisition excess bandwidth bit

field defines BW0 by scaling the value in the Profile x.y loop

bandwidth bit field by a power of two.

Assume the Profile x.y loop bandwidth bit field is set to yield a

0.0001 Hz (100 µHz) loop bandwidth. To set BW0 to 0.0512 Hz,

program Profile x.y fast acquisition excess bandwidth = 9.

BW0 = 0.0001 Hz × 2Profile x.y Fast Acquisition Excess Bandwidth

= 0.0001 Hz × 29

= 0.0001 Hz × 512

= 0.0512 Hz

In the preceding example, when the DPLL begins the signal

acquisition process, the starting loop bandwidth for the fast

acquisition sequence is 512 times wider than the final value.

After the DPLL acquires phase lock, the FACQ controller

tightens the loop bandwidth by a factor of two and waits for

phase lock. This bandwidth tightening process repeats until the

loop bandwidth reaches the value specified in the Profile x.y

loop bandwidth bit field. By using wider loop bandwidths

during the signal acquisition process, the fast acquisition feature

achieves lock much quicker than the DPLL. The phase lock

characteristic of the loop is subject to the DPLL lock detector

settings (see the DPLL Lock Detectors section).

FACQ Settling Time Control

Because each step in the FACQ process relies on phase lock

indication to continue on to the next step, it is important that

the phase lock indication not chatter. That is, a noisy reference

can cause the phase lock indicator to switch intermittently

between lock and unlock until the loop settles to a stable lock

condition. If the lock indicator chatters, it may cause the FACQ

controller to advance prematurely.

To help minimize the effect of a chattering phase lock indication,

the FACQ controller allows the user to specify a lock indication

settling time via the 3-bit unsigned Profile x.y fast acquisition

lock settle time bit field. The Profile x.y fast acquisition lock

settle time bit fields reside in Bits[D2:D0] of Register 0x1217,

0x1297, Register 0x12B7, Register 0x1617, Register 0x1637,

The value of the Profile x.y fast acquisition lock settle time bit field

tells the FACQ controller how long to observe a nonchanging

phase lock indication before moving on to the next step. Table 43

show the available settling time durations.

Table 43. FACQ Lock Detect Settling Time

Profile x.y Fast Acquisition Lock Settle

Time Bit Field Value

Settle Time

1 ms

10 ms

50 ms

100 ms

500 ms

1 sec

10 sec

50 sec

In operation, if the DPLL indicates a phase unlock within the

settling period, the FACQ controller does not advance to the

next step. Instead, it resets the settling timer, waits for the next

indication of phase lock and invokes the settling period again.

This process continues until the phase lock remains for the full

duration of the prescribed settling time.

FACQ Timeout Control

To prevent the FACQ controller from stalling because the DPLL

fails to reach a phase locked condition, the controller has a timeout

mechanism. That is, at each step in the fast acquisition process,

the FACQ controller waits for the DPLL to phase lock (and

settle), but only up to a user defined maximum amount of time.

The user specifies the maximum time for the FACQ controller

to wait for phase lock via the 3-bit unsigned Profile x.y fast

acquisition timeout bit field. The Profile x.y fast acquisition

timeout bit fields reside in Bits[D6:D4] of Register 0x1217,

0x1237, Register 0x1257, Register 0x1277, Register 0x1297,

0x1657, Register 0x1677, Register 0x1697, and Register 0x16B7.

The available timeout values appear in Table 44. If the FACQ

controller does not observe phase lock and settling within the

prescribed timeout interval, the FACQ controller automatically

advances to the next step in the fast acquisition process. When

the FACQ controller reaches the final bandwidth step and the

DPLL indicates phase lock within the specified settle time, the

FACQ controller sets the DPLLx FACQ done bit in Bit D5 of

controller reaches the last step due to a timeout, it does not set

the DPLLx FACQ done bit.

Table 44. FACQ Timeout

Profile x.y Fast Acquisition Timeout Bit Field Value

Settle Time

10 ms

50 ms

100 ms

500 ms

1 sec

10 sec

50 sec

100 sec

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