AD9545 datasheet(94/157 Pages) AD

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AD9545

Data Sheet

Rev. A | Page 94 of 157

averaging processor when the DPLL is not frequency locked.

The DPLLx pause history while phase slew limiting bit in

Bit D2 of Register 0x100F and Register 0x140F pauses or resets

the averaging processor when the phase slew limiter is slew

limiting (see the Phase Slew Rate Limit section).

The user may set any combination of these bits. Unlike the

averaging processor delay bits, however, when more than one of

these bits are Logic 1, the implementation of the delay behaves

as an OR function of the selected conditions. That is, when any

of the selected status conditions is satisfied, it resets or pauses

the averaging processor.

DELAY COMPENSATION

Overview

Delay compensation provides an automatic phase offset to the

DPLL to counteract temperature dependent delay variation.

Figure 78 is a block diagram of the DPLL and delay compensation

block. Delay compensation is only in effect while the DPLL is

active. Furthermore, the response of the delay compensation

output is subject to the loop bandwidth of the DPLL.

Delay compensation generates the temperature dependent time

offset value, Δt, based on a fifth degree polynomial, as shown in

Figure 78. The independent variable of the polynomial is

temperature (T). The five polynomial coefficients (C1 to C5),

which the user enters via the register map, scale corresponding

powers of T. Note that there is no need for a constant term (C0)

in the delay compensation block, because the DPLLx phase offset

bit field (see the DPLL Phase Offset Control section) serves that

function. The Δt computation implied by Figure 78 is

Δt





CiT

The temperature (T) input into the open-loop direct compensation

block originates from temperature sensor circuitry (see the

Temperature Sensor section). The user has the option of choosing

the temperature source: either the internal temperature sensor

(default) or the external temperature bit field (Register 0x2900

to Register 0x2901). When using the internal temperature

sensor, the device inherently uses the appropriate scaling units.

However, when using the external temperature option, the user

must provide the proper scaling (see the External Temperature

Source section for details).

DIGITAL

PHASE

DETECTOR

N-DIVIDER

DIGITAL

LOOP

FILTER

SYSTEM

CLOCK

NUMERIC

COEFFICIENTS

NCO

LOCK

DETECTORS

AD9545

FTW

PROCESSOR

DPLLx FREERUN

TUNING WORD

LOOP

CONTROLLER

XOA XOB

TDC

DPLLx

PHASE OFFSET

DPLLx PHASE

TEMPERATURE

COMPENSATION

FILTER

BANDWIDTH

∆t

APLL

TEXT

= BIT(S) IN THE REGISTER MAP

–

Figure 78. Delay Compensation

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