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Data Sheet

AD9545

Rev. A | Page 91 of 157

Calculate the value of the DPLLx phase slew limit rate bit field

necessary to limit the rate of change of phase (Δt/t) to 0.25 ppm

(2.5 × 10−7).

DPLLx Phase Slew Limit Rate = (Δt/t) × 1012

= (2.5 × 10−7) × 1012

= 250,000

= 0x0003D090 (hexadecimal)

TUNING WORD HISTORY

The DPLLs have a tuning word processor that handles the

application of tuning words to the NCO. The tuning word

processor embodies several of the functional blocks appearing

in Figure 71, including the loop controller, FTW processor, and

the switch. The NCO can receive tuning words from three

possible sources.

•

DPLLx freerun tuning word bit field

•

Digital loop filter

•

Tuning word averaging processor

This section focuses on the tuning word averaging processor,

which provides three digital outputs residing in the register map:

•

46-bit DPLLx tuning word history bit field

•

DPLLx history available status bit

•

DPLLx history updated bit

The DPLLx tuning word history bit field (where x is 0 or 1) resides

in Register 0x3103 to Register 0x3108 and Register 0x3203 to

0 or 1) resides in Bit D0 of Register 0x3102 and Register 0x3202.

The DPLLx history updated bit resides in Bit D2 of Register 0x3011

and Register 0x3016. The user also has access to the DPLLx

history available and DPLLx history update bits as a physical

logic level via an appropriately configured Mx pin.

The main purpose of the averaging processor is to compute an

average of tuning word samples when a DPLL translation profile

initially becomes active (but after expiration of any delays specified

by the delay element of the averaging processor as detailed the

Averaging Processor Delay section). After the averaging processor

collects a sufficient number of samples to allow a valid tuning word

average computation, it sets the DPLLx history available bit to

Logic 1. This setting indicates that the averaged tuning word

history is available. If the DPLL needs to switch to holdover

operation, the DPLL can use the averaged tuning word history

of the averaging processor. Otherwise, the DPLL uses the last

available tuning word from the loop filter or the value in the DPLLx

freerun tuning word bit field, depending on the configuration of

the averaging processor.

The averaging processor comprises three functional elements:

•

Delay

•

Windowed average

•

Continue or reset

These functional elements respond to user input via the register

map as explained in the Averaging Processor Delay section, the

Averaging Processor Windowed Average section, and the

Averaging Processor Continue or Reset section.

Averaging Processor Delay

By default, as soon as a translation profile becomes active (see the

Reference Switching section for what constitutes an active

translation profile), the tuning word processor resets the averaging

processor (and DPLLx history available bit) and the averaging

processor immediately starts processing tuning words from the

loop filter.

However, the user has access to two independent mechanisms to

impose a delay between when a translation profile becomes

active and when the averaging processor begins the tuning word

averaging process:

•

Any event dependent delay

•

A timed delay

By default, both mechanisms are inactive, implying no delay.

Event dependent delays take priority over time delays: first, any

of the three possible event dependent delay selections

programmed by the user, then the timed delay programmed by

the user. Until these delays expire, the tuning word processor

ignores incoming tuning words.

The status of the DPLL is the basis for the event-dependent

delay mechanism. To invoke the event dependent delay, write a

Logic 1 to any combination of the delay history control bits:

•

DPLLx delay history phase lock

•

DPLLx delay history frequency lock

•

DPLLx delay history until not slew limiting

These bits reside in Bits[D5:D3] of Register 0x100E and

The DPLLx delay history phase lock bit (where x is 0 or 1)

causes the averaging process to delay until the DPLL phase

locks. The DPLLx delay history frequency lock bit (where x is 0

or 1) causes the averaging process to delay until the DPLL

frequency locks. The DPLLx delay while not slew limiting bit

(where x is 0 or 1) causes the averaging process to delay until

the phase slew limiter ceases slew limiting, assuming slew

limiting occurs (see the Phase Slew Rate Limit section).

When more than one of the delay history control bits are Logic 1,

the implementation of the delay behaves as an AND function of

the selected conditions. That is, all the selected status conditions

must be satisfied before the averaging process begins. The status

conditions are real-time status indicators as they follow the

actual state of the DPLL. However, the moment all selected

status conditions are true, the averaging processor waits for the

prescribed hold off period to expire (assuming DPLLx history

hold off time ≠ 0) and starts the averaging process (even if any

of the status conditions become false after the averaging

processor starts averaging).

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