AD9545 datasheet(65/157 Pages) AD

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Data Sheet

AD9545

Rev. A | Page 65 of 157

The desired modulation period (PM) is 1 ms. Because the Qxy

modulation counter value must be an integer, however, it is not

always possible to produce the desired modulation period

exactly. In this example, the actual PM value is 1.0000210084 ms.

BALANCED AND UNBALANCED MODULATION

Modulation consists of periodic modulation events occurring at

regular intervals, PM, with a single modulation event spanning two

output clock cycles of the Q divider associated with the modulator.

The modulator applies the specified pulse width variation (per

the modulation step and Qxy modulation counter bit fields) to

one or both clock cycles of the modulation event. Modulation of

both clock cycles constitutes balanced modulation, whereas

modulation of only one clock cycle constitutes unbalanced

modulation.

To select the modulation type, use the enable Qxy single-pulse

modulator bit (where x is 0 or 1 and y is A, B or C) in Bit D2 of

whereas Logic 1 selects unbalanced modulation.

With balanced modulation, the modulator applies opposite

polarity to the modulation steps of the two consecutive cycles of

the modulation event (see Figure 56). As such, balanced

modulation maintains the average dc level of the waveform at

its nominal 50% amplitude point.

With unbalanced modulation, the modulator applies the

modulation step (Δt) to only the first pulse of the modulation

event, leaving the second pulse is unaltered (see Figure 57) and

resulting in a waveform with a dc level slightly less than its

nominal 50% amplitude point.

By default, the modulator applies negative polarity to Δt for the

first pulse of a modulation event (and positive Δt to the second

pulse if balance modulation is in effect). However, the user can

force alternate polarity via the Qxy modulator polarity bit (where x

is 0 or 1 and y is A, B, or C) in Bit D1 of Register 0x10CF to

Logic 0 (default) applies negative polarity to Δt for the first

pulse of a modulation event, whereas Logic 1 applies positive

polarity to Δt for the first pulse (see Figure 58). Note the positive

shift in dc offset for unbalanced modulation in this case.

TIME

NOMINAL

(50%)

NOMINAL

(50%)

–Δt

+Δt

MODULATION EVENT

DC = 50%

50%

FIRST

MODULATION

CYCLE

SECOND

MODULATION

CYCLE

Figure 56. Balanced Modulation Waveform

NOMINAL

(50%)

NOMINAL

(50%)

TIME

–Δt

DC < 50%

50%

SECOND PULSE

UNALTERED

MODULATION EVENT

FIRST

MODULATION

CYCLE

SECOND

MODULATION

CYCLE

Figure 57. Unbalanced Modulation Waveform

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