AD9545 datasheet(72/157 Pages) AD

72 / 157 page

AD9545

Data Sheet

Rev. A | Page 72 of 157

feedback signals and steering toward the reference clock edge

exhibiting the smallest relative phase offset.

Because a hitless acquisition undergoes frequency changes to

bring about phase alignment, there can be a significant phase

disturbance at the output while the loop locks to the phase of

the reference (even if the initial feedback and reference frequencies

are identical). The user can minimize this disturbance by placing a

limit on the DPLL output frequency excursion (caused by a

phase rate of change (δθ/δt) at its input) via the phase slew limit

feature (see the Phase Slew Rate Limit section). Furthermore,

the user can place a limit on the overall output frequency

excursion (due to both an input frequency offset and δθ/δt) by

using the frequency clamp feature (see the Tuning Word Offset

Clamp section).

Even during a hitless acquisition, the AD9545 builds out the

initial phase offset between the reference and feedback signals

(as though it were performing a phase buildout acquisition) to

help mitigate the disturbance at the output. However, unlike the

case of a phase buildout acquisition, the phase slew rate limiter

is operational during a hitless acquisition (see the Phase Slew

Rate Limit section for details on the phase slew rate limiter) and

applies slew rate limiting to the buildout phase transition as

needed.

For further information on how a PLL responds to switching

from one reference to another under hitless and phase buildout

operating modes see Application Note AN-1420.

Translation Mode Selection

PLL0 and PLL1 are capable of operating in any one of three

modes:

•

Phase buildout mode

•

Internal zero delay mode (hitless)

•

External zero delay mode (hitless)

The zero delay modes constitute hitless rather than phase

buildout operation. For details on each mode, see the Phase

Buildout Mode section, Internal Zero Delay (Hitless) Mode

section, and External Zero Delay (Hitless) Mode section.

The user selects the operating mode via the translation profile

registers. That is, each profile gives the user the option of selecting

any one of the three operating modes for that particular profile.

Each profile has two bits that allow the user to set the operating

mode for that profile (see Table 39). The first is the enable

Profile x.y hitless bit (where x is the PLL channel (0 or 1) and y

is the profile number (0 to 5)), which resides in Bit D0 of

0x1623, Register 0x1643, Register 0x1663, Register 0x1683, and

The second is the enable Profile x.y external zero delay bit

(where x is the PLL channel (0 or 1) and y is the profile number

(0 to 5)), which resides in Bit D1 of Register 0x1203, Register

0x1223, Register 0x1243, Register 0x1263, Register 0x1283,

0x1643, Register 0x1663, Register 0x1683, and Register 0x16A3.

Table 39. Frequency Translation Modes

Enable

Profile x.y

Hitless Bit

Enable Profile x.y

External Zero

Delay Bit

Translation Mode

Phase buildout

Not applicable

Internal zero delay

External zero delay

PHASE BUILDOUT MODE

Figure 63 shows the phase buildout configuration. When the

AD9545 switches from one input reference to another in phase

buildout mode, it does so with virtually no phase disturbance at

the output, which is possible because the AD9545 is able to

determine the phase offset between the old and new references

(see the Initial Phase Skew Refinement Steps section for more

detail). As such, the device can compensate for the time offset

of the new reference by adding the appropriate value to (or

subtracting from) timestamps generated by the TDC associated

with the new reference.

REFx

TDC

OUTxyN/

OUTxyP

REFX

TDC

AD9545

AUX

NCO 0/NCO 1

TDC

OTHER DPLL

FEEDBACK

TDC

DIGITAL CROSS

POINT MUX

TIME STAMP PROCESSOR,

DIGITAL LOOP FILTER,

TUNING WORD PROCESSOR

AND NCO

FEEDBACK

TDC

PFD

AND

LOOP

FILTER

M-DIVIDER

N-DIVIDER

TDC

OUTPUT

DISTRIBUTION

PHASE

BUILDOUT

DPLL

N + FRAC/MOD

MUX

SYSTEM

CLOCK

LFx

XOA XOB

APLL

VCO

÷2

Figure 63. Phase Buildout PLL Configuration

AD9545 датащи(PDF) 72 Page - Analog Devices

AD9545 датащи(HTML) 72 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL