AD9545 datasheet(90/157 Pages) AD

90 / 157 page

AD9545

Data Sheet

Rev. A | Page 90 of 157

Next, substitute fCLAMP into Equation 20:

DPLLx FTWOC = 236 × fCLAMP/fS

= 236 × 6250/(2.4 × 109)

= 178,957 (nearest integer)

= 0x02BB0D (hexadecimal)

The frequency clamping circuitry provides a status bit

indicating when it is actively clamping the frequency, namely,

the DPLLx frequency clamped bit (where x is 0 or 1) in Bit D1

of Register 0x3102 or Register 0x3202.

The DPLLx frequency clamped bit relates to the IRQ function

of the AD9545 via the DPLLx frequency clamp activated and

DPLLx frequency clamp deactivated bits (where x is 0 or 1). The

DPLLx frequency clamp activated bit (Bit D6 of Register 0x3010 or

changes state from not clamped to clamped. The DPLLx frequency

clamp deactivated bit (Bit D7 of Register 0x3010 or Register

0x3015) latches to Logic 1 when the frequency clamp changes state

from clamped to not clamped. Because these are latched bits, the

user must clear them via their corresponding IRQ clear bits

(Bits[D7:D6] of Register 0x200B and Register 0x2010) to obtain

visibility of subsequent state transitions of the frequency clamp.

PHASE SLEW RATE LIMIT

The digital phase detector uses the reference and feedback

TDCs to determine the associated phase error and pass it along

to the loop filter. In addition to the loop phase error, however,

other types of phase information can appear in the loop, for

example, phase offsets originating from any of the following:

•

Changes to the DPLLx phase offset bit field (Register 0x1015

to Register 0x1019 and Register 0x1415 to Register 0x1419)

•

Changes to the Profile x phase skew bit field (Register 0x080E

to Register 0x0810, Register 0x082E to Register 0x0830,

0x08D0, and Register 0x08EE to Register 0x08F0)

•

From the delay compensation block

•

As the result of a phase buildout operation

For certain phase sources, the DPLL provides a phase slew rate

limiting function (see Figure 77) that places an upper bound on

the rate of change of phase passed along to the loop filter. The

phase slew rate limiter mitigates the adverse effects of injecting

a large phase step into the loop by converting it to a phase ramp

with the maximum slope set by the user via the DPLLx phase

slew limit rate bit field (where x is 0 or 1) in Register 0x1011 to

The phase slew rate limiter provides the user with two status

bits: DPLLx phase slew limiter activated and DPLLx phase slew

limiter deactivated (where x is 0 or 1). The DPLLx phase slew

limiter activated bit (Bit D4 of Register 0x3010 or Register

0x3015) latches to Logic 1 when the phase slew rate limiter

changes state from not limiting to limiting. The DPLLx phase

slew limiter deactivated bit (Bit D5 of Register 0x3010 or

limiter changes state from limiting to not limiting. Because

these are latched bits, the user must clear them via Bits[D5:D4]

of Register 0x200B and Register 0x2010 to obtain visibility of

subsequent state transitions of the phase slew rate limiter.

DIGITAL

PHASE

DETECTOR

N-DIVIDER

DIGITAL

LOOP

FILTER

SYSTEM

CLOCK

NUMERIC

COEFFICIENTS

NCO

LOCK

DETECTORS

FTW

PROCESSOR

DPLLx FREERUN

TUNING WORD

LOOP

CONTROLLER

XOA XOB

AD9545

TDC

DPLLx PHASE

SLEW LIMIT RATE

TEXT

= BIT(S) IN THE REGISTER MAP

48-BIT

FTW

DIGITAL

CROSS

POINT

MUX

Figure 77. Phase Slew Limit Feature

The phase slew rate limiter operates only on phase transients

introduced by the following phase sources:

•

DPLLx phase offset bit field

•

Profile x phase skew bit field

•

initial phase correction due to activating a hitless mode

translation profile

That is, the DPLL only applies phase slew limiting under two

conditions. The first is a phase offset that exists at the start of a

reference acquisition. The second is phase offsets introduced by

the user via the DPLLx phase offset bit field and the Profile x

phase skew bit field.

The phase slew rate limit feature uses the 32-bit unsigned

DPLLx phase slew limit rate bit field (units are ps/sec or 10−12,

but accuracy is typically limited to approximately 50 ps/sec).

The phase slew rate limit feature is active for all DPLLx phase

slew limit rate values except zero, which disables the phase slew

rate limiter (this is not recommended). However, there is little

reason to disable the rate limiter. Instead, programming the rate

limiter to its maximum value imposes a slew rate limit correspond-

ing to a frequency shift in excess of 4000 ppm. Most applications do

not experience frequency transients exceeding 4000 ppm. The

default value of the DPLLx phase slew limit rate bit field

establishes a phase slew rate limit of 100,663,296 ps/s (which

equates to a maximum frequency shift of approximately 100 ppm).

The relationship between the desired phase slew rate limit, Δt/t,

and the value of the DPLLx phase slew limit rate bit field is as

follows:

DPLLx Phase Slew Limit Rate = (Δt/t) × 1012

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