AD9545 datasheet(18/157 Pages) AD

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AD9545

Data Sheet

Rev. A | Page 18 of 157

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Input Logic 1 Current

µA

Input Logic 0 Current

µA

SCLK

Input Logic 1 Voltage

VDDIOA − 0.4

Input Logic 0 Voltage

0.4

Input Logic 1 Current

µA

Input Logic 0 Current

µA

SDIO

As an Input

Input Logic 1 Voltage

VDDIOA − 0.4

Input Logic 0 Voltage

0.4

Input Logic 1 Current

µA

Input Logic 0 Current

µA

As an Output

Output Logic 1 Voltage

VDDIOA − 0.2

1 mA load current

Output Logic 0 Voltage

0.2

1 mA load current

SDO

Output Logic 1 Voltage

VDDIOA − 0.2

1 mA load current

Output Logic 0 Voltage

0.2

1 mA load current

Leakage Current

±1

µA

SDO inactive (high impedance)

TIMING

Valid for VDDIOA = 1.8 V, 2.5 V, and 3.3 V

SCLK

Clock Rate, 1/tCLK

MHz

Pulse Width High, tHIGH

Pulse Width Low, tLOW

SDIO to SCLK Setup, tDS

2.2

SCLK to SDIO Hold, tDH

SCLK to Valid SDIO and SDO, tDV

CSB to SCLK Setup, tS

1.5

CSB to SCLK Hold, tC

CSB Minimum Pulse Width High

tCLK

I2C Mode

Table 19.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SDA, SCL (AS INPUTS)

Valid for VDDIOA = 1.8 V, 2.5 V, and 3.3 V

Input Logic 1 Voltage

% of VDDIOA

Input Logic 0 Voltage

0.3 × VDDIOA

Input Current

−10

+10

µA

For VIN = 10% to 90% of VDDIOA

Hysteresis of Schmitt Trigger Inputs

1.5

% of VDDIOA

SDA (AS OUTPUT)

Output Logic 0 Voltage

0.2

IOUT = 3 mA

Output Fall Time from VIH Minimum

to VIL Maximum

20 + 0.1 × CB

250

10 pF ≤ CB ≤ 400 pF

TIMING

SCL Clock Rate

400

kHz

Bus Free Time Between a Stop and

Start Condition, tBUF

1.3

µs

Repeated Start Condition Setup

Time, tSU; STA

0.6

µs

Repeated Hold Time Start

Condition, tHD; STA

0.6

µs

After this period, the first clock pulse is

generated

Stop Condition Setup Time, tSU; STO

0.6

µs

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