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Data Sheet

AD9545

Rev. A | Page 83 of 157

DIGITAL

PHASE

DETECTOR

N-DIVIDER

DIGITAL

LOOP

FILTER

SYSTEM

CLOCK

NUMERIC

COEFFICIENTS

LOCK

DETECTORS

FTW

PROCESSOR

DPLLx FREERUN

TUNING WORD

LOOP

CONTROLLER

XOA XOB

AD9545

TDC

TEXT

= BIT(S) IN THE REGISTER MAP

48-BIT

FTW

DIGITAL

CROSS

POINT

MUX

Figure 71. DPLL Block Diagram

Figure 71 also shows the lock detectors (see the DPLL Lock

Detectors section). For details on the feedback divider, see the

DPLL Feedback Divider (N-Divider) section. For clarity, Figure

71 also shows the digital cross point mux and TDCs that feed

the digital phase detector (the TDCs convert the rising edges of

the input and feedback signals to numeric time stamps (see the

Time to Digital Converter (TDC) section for details)).

Although Figure 71 shows the N-divider connected directly to

the NCO output, this diagram is a simplification of the actual

feedback path (see Figure 62 in the Frequency Translation

Loops section). However, with regard to the operation and

control of the DPLL, this simplification is valid in the context of

the following paragraphs.

Frequency tuning of the DPLL is by virtue of a numerically

controlled oscillator (NCO), which employs a sigma-delta

modulator (SDM) architecture. The SDM has an internal

integer divider that divides down the system clock frequency

with the output of the divider constituting the output of the

NCO. The SDM effectively modulates the modulus of this

divider to produce an output frequency that is a fractionally

scaled down version of the system clock frequency based on an

input 48-bit FTW. Because the NCO is SDM-based, it employs

noise shaping that redistributes its modulation noise away from

the NCO output frequency (the APLL, which follows the DPLL,

suppresses the out of band modulation noise of the SDM).

The output frequency of the NCO (fNCO) depends on the

numeric value of the 48-bit FTW and the frequency of the

system clock (fS) per the following equation:

fNCO = fS × FTW/248

For a given fS and a desired fNCO, compute FTW as

FTW = round(248 × fNCO/fS)

(18)

where round() is a function to round the value in () to the

nearest integer.

The NCO automatically converts the 48-bit FTW into two

components: an integer part (INT) and a fractional part

(FRAC). The following constraints apply to INT and FRAC:

•

7 ≤ INT ≤ 13

•

0.05 ≤ FRAC ≤ 0.95

The constraints on INT and FRAC necessarily impose

limitations on the choice of FTW. To determine if FTW (as

prescribed by Equation 18) is valid, calculate INT and FRAC for

a given FTW, per Equation 19, where the operation on the left

side of the equation yields a number with an integer part and

fractional part (INT.FRAC).

248/FTW = INT.FRAC

(19)

For example, let fS = 2.30 GHz and fNCO = 245.76 MHz, which

yields the following:

FTW = round(248 × 245.76 MHz/2.30 GHz)

= 30,076,213,163,657

Use FTW to determine INT.FRAC as follows:

248/FTW = INT.FRAC

248/30,076,213,163,657 = 9.3587239583

That is, INT = 9 and FRAC = 0.3587239583, which satisfies the

7 ≤ INT ≤ 13 and 0.05 ≤ FRAC ≤ 0.95 constraint.

Although the preceding example validates FTW for the given fS

and fNCO, it does not necessarily validate FTW for a give

application. That is, the preceding example assumes fS and fNCO

are completely static values. However, fS is only as stable as the

oscillator or resonator at the XOA and XOB pins. Furthermore,

with the DPLL locked to an input reference signal, fNCO tracks

variations in the reference frequency. Therefore, the user must

assess variation on FTW for a given application. That is, there is

an upper and lower FTW value to consider, which leads to

upper and lower INT.FRAC values as well.

For example, assume in the preceding example that the

particular application causes FTW to vary by 0.5%, leading to

two FTW values that differ from 30,076,213,163,657 by 0.5%:

Lower FTW = 29,925,832,097,839

Upper FTW = 30,226,594,229,475

The upper and lower FTW values lead to the following

INT.FRAC values:

Lower INT.FRAC = 9.4057527219

Upper INT.FRAC = 9.3121631426

In this case, both INT values and both FRAC values satisfy the

constraints on INT and FRAC.

It is imperative that the upper and lower INT values be the

same. Otherwise, it implies that the upper and lower FTW

values cross an SDM integer boundary, which can lead to poor

spurious performance. There are two ways to remedy this problem.

The first, which is less workable, is to limit the variation on the

system clock frequency and the reference input frequency. The

second is to choose a new FTW value (and, by implication, a

new fNCO value). In either case, the goal is to constrain the

variation of the FTW such that it yields identical (and valid)

upper and lower INT values, as well as valid upper and lower

FRAC values.

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