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AD9545

Data Sheet

Rev. A | Page 62 of 157

Q DIVIDER

OUTPUT

CLOCK

OUTPUT

Q DIVIDER PERIOD (PER ITS INPUT CLOCK AND DIVIDE RATIO)

CLOCK SEGMENT = 6

GAP SEGMENT = 10

TRIGGER

TIME

PULSES

STALL

ABSENT PULSES

END OF

BURST

END OF

FINAL

BURST

Figure 53. Stalling a Periodic Gapped Clock Signal

N-Shot Triggering

The N-shot trigger signal originates from one of two sources:

•

N-shot request Channel x bit

•

External signal applied via the Mx pins

Whether using the N-shot request Channel x bit or an external

Mx pin signal, a Logic 1 constitutes a trigger event. In general,

the user must apply Logic 1 to trigger the N-shot generators,

then return the trigger source to Logic 0. Otherwise, holding

the trigger source in a Logic 1 state indefinitely may lead to

unwanted retriggering of the N-shot generators on subsequent

distribution synchronization events (see the Distribution

Output Clock Synchronization section).

The N-shot generators respond to the trigger signal based on

the N-shot request mode bit. As described in the N-Shot

Pattern Generation section, this bit makes the trigger input of

the N-shot generators edge or level sensitive for generating burst

or periodic gapped clock signals, respectively (per Figure 51 and

Figure 52).

The trigger mechanism for delivering a trigger signal to the

N-shot generators appears in the upper left section of Figure 48.

The N-shot generators support two triggering methods: direct

and retimed.

To select the desired triggering method, use the enable N-shot

retime bit in Register 0x10D6, Bit 0, and Register 0x14D6, Bit 0.

Logic 0 (default) selects direct, whereas Logic 1 selects retimed.

For the direct triggering method, the trigger signal applies

directly to the trigger input of the N-shot generators. Thus, the

trigger signal is the trigger event.

Note that in the following paragraphs, the terms slowest and

fastest appear in reference to the output clock signal of the

Q dividers. Slowest and fastest refers to the largest and smallest

Qxy phase value, respectively (see the Initial Phase Offset section).

For the retimed triggering method, the trigger signal routes to

the N-shot retime block instead of directly to the N-shot

generators. The rising edge of the trigger signal initializes the

retiming block such that it waits for the rising edge of the

slowest of all the Q dividers enabled for N-shot operation (user

specified). The trigger signal, qualified by the slowest Q divider

rising edge, constitutes a retimed trigger event. The retiming

block sends a trigger signal to the N-shot generators coincident

with the retimed trigger event as shown in Figure 61.

The retimed trigger event occurs with a latency of three rising

edges of the slowest Q divider. Furthermore, when using the

retimed trigger mechanism, the associated Q dividers must have

a divide ratio of at least 32. A minimum setup time is required

between the retiming output (slowest) and the subsequent

N-shot enabled output (fastest), which is 48 Q divider input

half-cycles.

The retimed trigger is on the rising edge of the slowest N-shot

enabled Q divider to accommodate multiple N-shot generators

producing multiple output clocks. Using the rising edge of the

slowest Q divider output as a retiming mark ensures that all N-

shot generators begin clocking with the fastest output being the

earliest of the group, even when the Q dividers have different

programmed phase offsets and regardless of when the N-shot

request occurs.

The device automatically selects the appropriate N-shot enabled

Q divider for trigger retiming, such that the output with the

largest Qxy phase value is always the retiming clock.

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