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AD9545 датащи(PDF) 9 Page - Analog Devices

номер детали AD9545
подробное описание детали  Quad Input, 10-Output, Dual DPLL/IEEE 1588 1 pps Synchronizer and Jitter Cleaner
PDF  157 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD9545 датащи(HTML) 9 Page - Analog Devices

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Data Sheet
AD9545
Rev. A | Page 9 of 157
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
Incremental Power Dissipation
Complete DPLL/APLL On/Off
200
mW
Based on the Typical Configuration specification; the values in
this section indicate the change in power due to the indicated
operation relative to the Typical Configuration specification;
the blocks, when powered down, consist of one reference input,
one DPLL, one APLL, two channel dividers, and two output
drivers
Input Reference On/Off
Differential (AC-Coupled Mode)
20
mW
fREF = 19.44 MHz (see Figure 29)
Differential (DC-Coupled Mode)
21
mW
fREF = 19.44 MHz (see Figure 30)
Single-Ended
13
mW
fREF = 19.44 MHz
Output Distribution Driver On/Off
At 156.25 MHz
15 mA Mode
30
mW
12 mA Mode
23
mW
7.5 mA Mode
15
mW
Auxiliary DPLL On/Off
1
mW
Auxiliary Numerically Controlled
Oscillator (NCO) to Mx Pin On/Off
1
mW
Fundamental set to 50 kHz
Auxiliary Time-To-Digital Converters
(TDC) Input from Mx Pin On/Off
1
mW
Input frequency = 10 MHz, auxiliary TDC rate = 200 kHz



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