AD9545 datasheet(13/157 Pages) AD

13 / 157 page

Data Sheet

AD9545

Rev. A | Page 13 of 157

DPLL PHASE CHARACTERISTICS

Table 7.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

MAXIMUM OUTPUT PHASE

PERTURBATION

Assumes a jitter free reference; satisfies Telcordia GR-1244

requirements; 0 ppm frequency difference between references;

reference switch initiated via register map (see the AD9545 Register

Map Reference Manual) by faulting the active reference input

Phase Refinement Disabled

50 Hz DPLL loop bandwidth; normal phase margin mode; frequency

translation = 19.44 MHz to 155.52 MHz; 49.152 MHz signal generator

used for system clock source

Peak

±20

±140

Steady State

Phase Buildout Operation

±18

±125

Hitless Operation

Phase Refinement Enabled

50 Hz DPLL loop bandwidth; high phase margin mode; phase

refinement iterations = 4; frequency translation = 19.44 MHz to

155.52 MHz; 49.152 MHz signal generator used for system clock source

Peak

±5

±40

Steady State

Phase Buildout Operation

±4

±35

Hitless Operation

PHASE SLEW LIMITER

0.001

250

µs/sec

See the AN-1420 Application Note

DISTRIBUTION CLOCK OUTPUTS

Table 8.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DIFFERENTIAL MODE

All testing is both ac-coupled and dc-coupled

Output Frequency

Frequency range determined by driver

functionality; actual frequency synthesis may be

limited by the APLL VCO frequency range

Common Mode Logic (CML)

500 × 106

Terminated per Figure 33

High Speed Current Steering

Logic (HCSL)

500 × 106

Terminated per Figure 32

Differential Output Voltage Swing

Voltage between output pins measured with

output driver static; peak-to-peak differential

output amplitude is twice that shown when driver

is toggling and measured using a differential probe

Output Current = 7.5 mA

HCSL

312

368

402

Terminated per Figure 32

CML

257

348

408

Terminated to VDD (nominal 1.8 V) per Figure 33

Output Current = 15 mA

HCSL

631

745

809

Terminated per Figure 32

CML

578

729

818

Terminated to VDD (nominal 1.8 V) per Figure 33

Common-Mode Output Voltage

Output Current = 7.5 mA

HCSL

155

184

201

Terminated per Figure 32

CML

VDD − 208

VDD − 188

VDD − 169

Terminated to VDD (nominal 1.8 V) per Figure 33

(maximum common-mode voltage case occurs at

the minimum amplitude)

Output Current = 15 mA

HCSL

316

372

405

Terminated per Figure 32

CML

VDD − 416

VDD − 371

VDD − 327

Terminated to VDD (nominal 1.8 V) per Figure 33

(maximum common-mode voltage case occurs at

the minimum amplitude)

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