AD9545 datasheet(39/157 Pages) AD

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Data Sheet

AD9545

Rev. A | Page 39 of 157

REFERENCE CLOCK INPUT RECEIVERS

REFERENCE CLOCK RECEIVERS OVERVIEW

The AD9545 has four reference clock input pins supporting up

to four reference clock signals. Two of the four pins designate

the A reference input path, and the other two pins designate the

B reference input path. Both the A and B reference inputs are

configurable as either one differential input or as two single-ended

inputs, allowing the AD9545 to handle up to four reference

clock signals. Each A and B reference input path has a dedicated

REFx input mode bit (where x is A or B) for selecting single-

ended or differential modes in Bit D0 of Register 0x0300 and

and Logic 1 differential mode). To accommodate input signals

with slow rising and falling edges, both the differential and

single-ended input receivers employ hysteresis. Hysteresis also

ensures that a disconnected or floating input does not cause the

receiver to oscillate.

SINGLE-ENDED MODE

When configured for single-ended operation, the input

receivers accommodate either ac- or dc-coupled input signals

•

AC-coupled interface

•

DC-coupled 1.2 V CMOS

•

DC-coupled 1.8 V CMOS

•

Internal pull-up resistor

For programming the desired coupling, use the 2-bit REFx

single-ended mode bit fields (where x is A, AA, B, or BB) in

Bits[D7:D4] of Register 0x0300 and Register 0x0304. These bit

fields are only effective when single-ended mode is in effect.

Table 27 shows the settings for the single-ended mode bit fields.

Table 27. REFx Single-Ended Mode Bit Field Settings

REFx Single-Ended

Mode (Decimal)

Description

AC-coupled interface

DC-coupled 1.2 V CMOS

DC-coupled 1.8 V CMOS

Internal pull-up resistor (disable

pull-down resistor)

The ac-coupled mode has an internal bias termination

equivalent to a 0.6 V dc source with a 23.5 kΩ series resistance.

The dc-coupled modes have a 47 kΩ resistor connected to

ground. The internal pull-up mode has a 47 kΩ resistor

connected to 1.2 V.

Single-Ended DC-Coupled Interface (1.2 V or 1.8 V CMOS)

Refer to Figure 25 for connecting a 1.2 V or 1.8 V CMOS driver to

a reference input. Be sure to select the corresponding DC-coupled

1.2 V or 1.8 V CMOS mode via the appropriate REFx single-ended

mode bit field (Bits[D7:D4] of Register 0x0300 and Register

0x0304).

Single-Ended DC-Coupled Internal Pull-Up Resistor

Refer to Figure 27 for connecting an open-collector or open-drain

driver to a reference input. Be sure to select the internal pull-up

mode via the appropriate REFx single-ended mode bit field

(Bits[D7:D4] of Register 0x0300 and Register 0x0304), which

provides an internal pull-up resistor (~47 kΩ) to 1.2 V.

Single-Ended AC-Coupled Interface

Refer to Figure 26 to ac-couple a driver to a reference input. Be

sure to select the ac-coupled interface mode via the appropriate

REFx single-ended mode bit field (Bits[D7:D4] of Register

0x0300 and Register 0x0304), which provides the appropriate

internal bias network.

DIFFERENTIAL MODE

When configured for differential operation, the input receivers

accommodate either ac- or dc-coupled input signals

•

AC-coupled

•

DC-coupled

•

DC-coupled LVDS

For programming the desired coupling, there are two bit fields: one

for the REFA and REFAA differential inputs and one for the REFB

and REFBB differential inputs. Use the REFx differential mode bit

field (where x is A or B) in Bits[D3:D2] of Register 0x0300 and

effective when the corresponding differential mode is in effect.

Table 28 shows the settings for the single-ended mode bit fields.

Table 28. REFx Differential Mode Settings

REFx Differential Mode

(Decimal)

Description

AC-coupled

DC-coupled

DC-coupled LVDS

The ac-coupled mode has an internal bias termination on each

differential input pin, which has a Thevenin equivalent of a

0.6 V dc source in series with a 23.5 kΩ series. The dc-coupled

mode expects the external driver to provide a 0.6 V common-

mode bias. The dc-coupled LVDS mode expects a 1.2 V

common-mode source with LVDS signal levels – as delivered by

a standard LVDS driver.

For differential mode operating frequencies in excess of

10.24 MHz, use the ac-coupled differential mode and connect

the reference input clock signal to the reference input pins

through a series dc blocking capacitor. For differential mode

operating frequencies below 10.24 MHz, use dc-coupled

differential mode. For direct connection of a low frequency

(below 10.24 MHz) LVDS input reference source, use dc-

coupled LVDS mode, which provides the necessary level

shifting.

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