AD9545 datasheet(52/157 Pages) AD

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AD9545

Data Sheet

Rev. A | Page 52 of 157

To remedy this uncertainty, the user can force a driver pair to a

known state by means of the various driver reset bits.

Bit D2 of Register 0x2101 allows the user to reset all the driver

pairs of Channel 0. Bit D2 of Register 0x2201 allows the user to

reset all the driver pairs of Channel 1. The user can reset individual

driver pairs via Bit D5 of Register 0x2102 to Register 0x2104

and Register 0x2202 to Register 0x2203.

When a driver pair is in a differential configuration, resetting

the driver pair forces the OUTxyP driver to a Logic 0 state and

the OUTxyN driver to a Logic 1 state. When a driver pair is in a

single-ended configuration, resetting the driver pair forces the

OUTxyP and OUTxyN drivers to a Logic 0 state.

OUTPUT MUTING

Manual Output Muting

To mute all the drivers associated with PLL Channel 0 or

Channel 1 use the mute all Channel x drivers bit (Logic 0 by

default) in Bit D1 of Register 0x2101 and Register 0x2201. To

mute individual drivers use the dedicated mute OUTxy bits

(where x is 0 or 1 and y is A, AA, B, BB, C, or CC) in Bits[D3:D2]

of Register 0x2102 to Register 0x2104 and Register 0x2202 to

default. The mute bits allow the user to turn off the clock signal

at the output pins without affecting the input clock signal to the

driver.

Automatic Output Unmuting

Automatic unmuting works in conjunction with the autosync

function (see the Autosync Trigger section). Part of the

synchronization sequence involves synchronously unmuting the

output drivers. The AD9545 provides the user options for the

timing of the unmuting of the output drivers.

To select the automatic unmute conditions, use the 2-bit DPLLx

autounmute mode bit field (where x is 0 or 1) in Bits[D1:D0]

of Register 0x10DC and Register 0x14DC. Table 34 shows the

autounmute conditions invoked by these bits. Note that

autounmute control applies to PLL Channel 0 and PLL

Channel 1, independently.

Table 34. Autounmute Conditions

DPLLx Autounmute Mode

Bit Field Value (Decimal)

Automatic Unmute Condition

Immediate (default)

Upon activation of a hitless profile

Upon phase lock (hitless mode only)

Upon frequency lock (hitless

mode only)

When DPLLx autounmute mode = 0 (default), the drivers

unmute immediately upon release of the sync request. When

DPLLx autounmute mode = 1, the drivers do not unmute until

release of the sync request and subsequent activation of a

hitless/zero delay profile. When DPLLx autounmute mode = 2,

the drivers do not unmute until release of the sync request and

subsequent phase lock of the appropriate PLL channel

(assuming a hitless/zero delay profile). When DPLLx

autounmute mode = 3, the drivers do not unmute until release

of the sync request and subsequent frequency lock of the

appropriate PLL channel (assuming a hitless/zero delay profile).

The user can also selectively opt out of the autounmuting

feature on a per output basis. The mask OUTxy autounmute

bits (Logic 0 by default) accomplish this function (where x is 0

or 1 and y is A, AA, B, BB, C, or CC) in Bits[D7:D2] of

After an automute event occurs for a particular PLL channel,

the user can clear the automute state by setting the associated

Channel x automute clear bit (Logic 0 by default) in Bit D4 of

generally unnecessary, because the device automatically clears

the automute state whenever the user changes the DPLLx

autounmute mode bit field and issues an IO_UPDATE operation.

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