AD9545 datasheet(2/157 Pages) AD

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AD9545

Data Sheet

Rev. A | Page 2 of 157

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 5

Functional Block Diagram .............................................................. 7

Specifications..................................................................................... 8

Supply Voltage............................................................................... 8

Supply Current.............................................................................. 8

Power Dissipation......................................................................... 8

System Clock Inputs, XOA and XOB....................................... 10

Reference Inputs ......................................................................... 11

Reference Monitors .................................................................... 12

DPLL Phase Characteristics...................................................... 13

Distribution Clock Outputs ...................................................... 13

Time Duration of Digital Functions ........................................ 14

Digital PLL (DPLL0, DPLL1) Specifications .......................... 15

Digital PLL Lock Detection Specifications ............................. 15

Holdover Specifications............................................................. 16

Analog PLL (APLL0, APLL1) Specifications.......................... 16

Output Channel Divider Specifications .................................. 16

Auxiliary Circuit Specifications................................................ 17

System Clock Compensation Specifications........................... 17

Temperature Sensor Specifications .......................................... 17

Serial Port Specifications ........................................................... 17

Logic Input Specifications (RESETB, M0 to M6) .................. 19

Logic Output Specifications (M0 to M6) ................................ 20

Jitter Generation (Random Jitter) ............................................ 20

Phase Noise ................................................................................. 21

Absolute Maximum Ratings.......................................................... 24

Thermal Resistance .................................................................... 24

ESD Caution................................................................................ 24

Pin Configuration and Function Descriptions........................... 25

Typical Performance Characteristics ........................................... 27

Terminology .................................................................................... 31

Theory of Operation ...................................................................... 32

Input/Output Termination Recommendations .......................... 33

System Clock Inputs................................................................... 33

Reference Clock Inputs.............................................................. 33

Clock Outputs ............................................................................. 34

System Clock PLL........................................................................... 36

System Clock PLL Overview .................................................... 36

System Clock Input Frequency Declaration ........................... 36

System Clock Source.................................................................. 36

2× Frequency Multiplier............................................................ 37

Prescale Divider.......................................................................... 37

Feedback Divider........................................................................ 37

System Clock PLL Output Frequency ..................................... 37

System Clock PLL Lock Detector............................................. 37

System Clock Stability Timer.................................................... 37

System Clock Calibration.......................................................... 37

System Clock Stability Compensation..................................... 38

Reference Clock Input Receivers.................................................. 39

Reference Clock Receivers Overview ...................................... 39

Single-Ended Mode.................................................................... 39

Differential Mode ....................................................................... 39

Reference Dividers (R Dividers)................................................... 41

Reference Monitor.......................................................................... 42

Reference Monitor Overview ................................................... 42

Reference Monitor State Machine............................................ 43

Reference Monitor Controls ..................................................... 43

Monitor Time Base..................................................................... 44

Reference Period Jitter Estimation........................................... 45

Reference Monitor Decision Time........................................... 45

Reference Validation .................................................................. 45

Reference Monitor Reset ........................................................... 46

Reference Demodulator................................................................. 47

Reference Demodulator Overview .......................................... 47

Demodulator Enable.................................................................. 47

Demodulator Delay.................................................................... 48

Demodulator Polarity ................................................................ 48

Automatic Polarity Detection ................................................... 48

Demodulator Sensitivity............................................................ 49

Demodulator Persistence .......................................................... 49

Demodulator Bandwidth .......................................................... 49

Distribution Clock Output Drivers.............................................. 50

Distribution Clock Output Drivers Overview ....................... 50

Output Current Control ............................................................ 50

Output Mode Control................................................................ 50

Output Driver Configurations.................................................. 50

Output Driver Reset................................................................... 51

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