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AD9545

Data Sheet

Rev. A | Page 76 of 157

SOURCE PROFILES

SOURCE PROFILES OVERVIEW

The source profiles give the user a method to define how an

input source, when selected by a DPLL channel via the active

translation profile, interacts with the DPLL. The register map

provides access to the eight source profiles via Register 0x0800

to Register 0x08F1. Each source profile gives the user control of

the following parameters:

•

DPLL phase lock detector

•

DPLL frequency lock detector

•

Phase step limit

•

Skew adjustment

•

Initial phase skew refinement steps

The source profiles relate to the Profile x.y reference source

selection bit field associated with the DPLL translation profiles

found in Register 0x1200 to Register 0x12B7 and Register 0x1600

to Register 0x16B7. That is, a translation profile attaches to a

particular source profile based on the value of the associated

Profile x.y reference source selection bit field of the translation

profile (see the Translation Profiles section).

DPLL PHASE/FREQUENCY LOCK DETECTOR

See the DPLL Lock Detectors section for details concerning the

phase and frequency detectors of the DPLL.

PHASE STEP LIMIT

Although the AD9545 has the ability to switch between

multiple reference inputs, some applications use only one input

and handle reference switching externally (see Figure 66). This

arrangement forfeits the ability of the AD9545 to mitigate the

output disturbance associated with a reference switchover,

because the reference switchover is not under the control of the

AD9545. However, the AD9545 offers a phase transient

threshold detection feature to help identify when an external

reference switchover occurs and act accordingly.

AD9545

REFx

REFERENCE 1

REFERENCE 2

SWITCHOVER

CONTROL

Figure 66. External Reference Switching

Phase transient threshold detection works by monitoring the

output of the DPLL phase detector for phase transients but in a

manner that is somewhat jitter tolerant. Otherwise, the phase

transient threshold detector is prone to false positives.

To activate the phase transient threshold detection, program the

32-bit unsigned Profile x phase step threshold bit field (where x

is a value from 0 through 7 corresponding to a particular source

profile) in registers starting with Address 0x080A, Address 0x082A,

Address 0x084A, Address 0x086A, Address 0x088A, Address

0x08AA, Address 0x08CA, and Address 0x08EA.

The default value is zero, which disables the phase transient

threshold detector. A nonzero value denotes the desired phase

step threshold (ΦTHRESH) in units of picoseconds per the

following equation.

ΦTHRESH

= Profile x Phase Step Threshold × 10−12

(14)

The phase transient threshold detector is not active unless the

DPLL indicates frequency locked status.

Determine the value of the Profile x phase step threshold bit

field necessary for a 12 ns limit (that is, ΦTHRESH = 12 × 10−9).

Solving Equation 14 for Profile x phase step threshold yields

Profile x Phase step Threshold = ΦTHRESH/10−12

= (12 × 10−9)/10−12

= 12,000

= 0x00002EE0 (hexadecimal)

To reduce the likelihood of threshold violations induced by

jitter, the user must choose ΦTHRESH to be at least two times the

expected rms jitter (σJITTER) associated with the input reference

signal.

ΦTHRESH

≥ 2 × σJITTER

(15)

As such, in the previous example with for Profile x phase step

threshold = 12,000, an input signal with 12 ns rms jitter is likely

to produce false positives, because it violates the inequality in

Equation 15. To reduce the likelihood of a false positive, the

inequality in Equation 15 implies that Profile x phase step

threshold = 24,000 is a better choice. However, even with a

value of 24,000, there is still a slight probability of a jitter sample

exceeding 2 × σJITTER. As such, scaling σJITTER by four to six is an

even better choice.

When a phase transient occurs that exceeds the prescribed

value, one or both of the following two events occur, depending

on the state of the enable step detect reference fault bit in Bit D7

of Register 0x2105 and Register 0x2205:

•

The DPLL initiates a new acquisition sequence

•

The reference monitor is reset

When the enable step detect reference fault bit is Logic 0

(default), detection of a phase step causes only the first event to

occur. By initializing a new DPLL acquisition sequence, the

DPLL can take advantage of the fast acquisition feature (see the

DPLL Fast Acquisition (FACQ) Options section), assuming it is

active, which is especially helpful for very low loop bandwidth

applications. In addition, a new acquisition manages the impact

of the phase step by either building out the phase or slewing to

the new phase in a hitless manner.

When the enable step detect reference fault bit is Logic 1,

detection of a phase step causes both events to occur. Because

exceeding the phase step threshold in this case implies an

external switch to a new reference, resetting the reference

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