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AD9545

Data Sheet

Rev. A | Page 32 of 157

THEORY OF OPERATION

Figure 41 summarizes the fundamental building blocks of the

AD9545. The core of the device comprises two independent

PLLs, PLL0 and PLL1. The primary function of the device is to

accept a clock signal at one of the REFx inputs and deliver it to

one (or more) of the OUTxyP and OUTxyN outputs via the two

independent pathways provided by PLL0 and PLL1.

In addition, the device provides a frequency translation between

the input and output by a programmed ratio, while at the same

time suppressing the jitter carried by the input signal.

The AD9545 synthesizes its system clock via a system clock

PLL, which upconverts the frequency applied to the system

clock input pins, XOA and XOB. The system clock input pins

accept frequencies from 20 MHz to 300 MHz from an external

clock source. Alternatively, the user can connect a crystal

resonator (25 MHz to 60 MHz) directly across the XOA and

XOB pins. The AD9545 primary time base for all of its time

keeping functions is the system clock.

The AD9545 supports up to four reference input clock signals with

frequencies ranging from 1 Hz to 750 MHz. Each reference input

has a dedicated reference monitor for detecting if the reference

signal is lost or compromised. The AD9545 can detect reference

faults and automatically switch to one of the other valid reference

inputs with user-programmable priority.

The DPLL portion of each PLL channel includes a programmable

digital loop filter with extremely low loop bandwidth capability.

Low loop bandwidth capability enables a significant reduction

of jitter transfer from the reference input to the output. Each

DPLL provides precise frequency translation by means of a 48-bit

NCO capable of generating clock signals in the range of 162 MHz

to 350 MHz. Furthermore, both DPLLs enable support of

manual or automatic transition to holdover operation.

Holdover operation constitutes the device generating an output

frequency synthesized from the system clock (as opposed to

translating a frequency from a reference input to an output).

During holdover operation, the AD9545 continuously provides

an output clock signal while the system clock is present. The

AD9545 is also capable of setting the holdover output frequency

based on a time average of the output frequency history prior to

the transition to holdover operation.

The output signal from the DPLL routes to the input of the APLL,

which upconverts the signal to a range of 2.424 GHz to 3.232 GHz

or 3.232 GHz to 4.040 GHz (APLL0 or APLL1, respectively). The

APLL VCO output frequency is downconverted by a factor of three

prior to delivery to the clock distribution section.

The clock distribution section consists of a bank of dividers (Q)

and output drivers dedicated to each output pin. The PLL0

channel has six Q divider/driver units, whereas the PLL1

channel has four Q divider/driver units. Each Q divider has 32-

bit programmable division depth and programmable phase

offset control. The drivers operate up to 500 MHz and are

configurable as single-ended or differential output with

adjustable output current (7.5 mA, 12 mA, or 15 mA).

The user also has access to two independent auxiliary NCOs.

These provide for internally generated frequencies up to 65 kHz

with a tuning resolution of 2−40 Hz (approximately 1 pHz). The

user can also access two auxiliary TDCs, which generate high

resolution time stamps associated with the rising edges of an

input signal applied to one of the Mx pins.

The AD9545 includes an integrated temperature sensor and

system clock compensation circuitry, which allows the device to

adjust automatically for frequency drift errors associated with

the system clock source.

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