AD9545 datasheet(69/157 Pages) AD

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Data Sheet

AD9545

Rev. A | Page 69 of 157

Q Divider Clock Source Selection section) for a subset of the

device outputs.

AUTOSYNC TRIGGER

Although the AD9545 provides the user with the ability to

synchronize the distribution outputs via a manual sync trigger,

it is not a recommended action. Instead, the AD945 provides an

autosync trigger feature that applies only after meeting certain

conditions, which overcomes potential usability issues

associated with manual trigger scenarios. In fact, the immediate

autosync mode (see Table 37) is an effective replacement for

manual sync triggering.

The user selects the desired autosync trigger conditions via the

2-bit autosync mode bit field in Bits[D1:D0] of Register 0x10DB

and Register 0x14DB. Autosync control applies to PLL Channel 0

and PLL Channel 1, independently. Table 37 shows the

selectable autosync conditions.

Table 37. Autosync Trigger Selections

Autosync Mode Bit Field Value

Autosync Trigger Condition

Disabled (default)

Immediate

On DPLL phase lock

On DPLL frequency lock

Autosync enables the AD9545 to execute a distribution

synchronization sequence without any user intervention. The

nonzero autosync selections specify conditions for generating

an autosync trigger.

When autosync mode = 0 (default), only manual or

autoreconfiguration triggers are possible. When autosync mode

≠ 0, the autosync trigger feature is in effect.

When autosync is active (autosync mode ≠ 0), nothing happens

until the system clock PLL indicates locked. The autosync

mechanism then enters an autosync trigger detection loop

awaiting the specified autosync event. When autosync mode =

1, the autosync event constitutes the indication of locked status

by the system clock PLL. When autosync mode = 2, the autosync

event constitutes an indication of phase lock by the DPLL.

When autosync mode = 3, the autosync event constitutes an

indication of frequency lock.

Note that after the autosync trigger occurs for a particular PLL

channel, the autosync trigger generation sequence terminates.

Subsequent autosync sequences on the same PLL channel are

not possible unless the user sets the associated Clear Channel x

autosync one-shot bit (Logic 0 by default) in Bit D0 of Register

0x2107 or Register 0x2207, or by updating the Autosync mode

bits in Bits[D1:D0] of Register 0x10DB or Register 0x14DB.

REFERENCE SYNCHRONIZATION

Output clock synchronization establishes a coincident starting

time among output clocks (usually on a per PLL channel basis).

Output clock synchronization, however, is generally asynchronous

with respect to input reference clock signal edges. The reference

synchronization feature allows the user to make a rising edge of

the input reference clock an additional gating item for synchroniza-

tion of the output clocks. Reference synchronization establishs a

small fixed phase relationship (~30 ns) between the input and

output clocks (assuming the output clock frequency is an

integer multiple of the input reference frequency). Establishing

an initial fixed phase relationship between the input and output

clocks minimizes the DPLL acquisition time by making it

deterministic rather than completely random.

The reference synchronization feature requires a hitless profile

be active when reference synchronization is in effect. The

reference synchronization feature does not function with a

phase buildout profile.

Like most of the other synchronization features, reference

synchronization applies on a per PLL channel basis. To enable

the reference synchronization feature, use the enable DPLLx

reference sync bit (where x is 0 or 1) in Bit D2 of Register 0x10DB

and Register 0x14DB. Setting the enable DPLLx reference sync

bit (Logic 0 by default) enables reference synchronization of

those outputs associated with the corresponding PLL channel.

When using reference synchronization in conjunction with

autosync mode (that is, autosync mode = 1, 2, or 3), be sure to

program enable DPLLx reference sync = 1 and assert the I/O_

UPDATE bit prior to programming autosync mode = 1, 2, or 3.

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