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AD9545

Data Sheet

Rev. A | Page 20 of 157

LOGIC OUTPUT SPECIFICATIONS (M0 TO M6)

Table 21.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LOGIC OUTPUTS (M0 to M6)

Valid for 3.3 V ≥ VDDIOx ≥ 1.8 V; VDDIOA applies for the M5 and

M6 pins; VDDIOB applies for M0 to M4; normal (default) output

drive current setting for M0 through M6

Frequency Range

MHz

Output Voltage

High, VOH

VDDIOx − 0.6

Load current = 10 mA

VDDIOx – 0.2

Load current = 1 mA

Low, VOL

0.6

Load current = 10 mA

0.2

Load current = 1 mA

JITTER GENERATION (RANDOM JITTER)

Table 22.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

JITTER GENERATION

System clock doubler enabled; high phase margin mode enabled;

there is not a significant jitter difference between driver modes

Channel 0—DPLL0, APLL0

Channel 1 powered down

RMS Jitter (12 kHz to 20 MHz)

Configuration 1—155.52 MHz

223

Device configuration: fOSC = 52 MHz crystal, fREF = 38.88 MHz, fVCO =

2488.32 MHz, fOUT = 155.52 MHz, DPLL BW = 50 Hz, phase buildout

operation

Configuration 2—245.76 MHz

220

Device configuration: fOSC = 52 MHz crystal, fREF = 30.72 MHz, fVCO =

2457.6 MHz, fOUT = 245.76 MHz, DPLL BW = 50 Hz, internal zero delay

operation

Configuration 3—491.52 MHz

235

Device configuration: fOSC = 52 MHz crystal, fCOMP = 19.2 MHz

temperature compensated crystal oscillator (TCXO), BWCOMP = 50 Hz,

fREF = 1 Hz, fVCO = 2949.12 MHz, fOUT = 491.52 MHz, DPLL BW = 50 mHz,

phase buildout operation

Configuration 4—125 MHz

213

Device configuration: fOSC = 52 MHz crystal, fCOMP = 19.2 MHz TCXO,

BWCOMP = 50 Hz, fREF = 125 MHz, fVCO = 2500 MHz, fOUT = 125 MHz, DPLL

BW = 0.1 Hz, phase buildout operation

Configuration 5—312.5 MHz

217

Device configuration: fOSC = 52 MHz crystal, fREF = 25 MHz, fVCO = 2500

MHz, fOUT = 312.5 MHz, DPLL BW = 50 Hz , phase buildout operation

Configuration 6—174.7030837 MHz

230

Device configuration: fOSC = 52 MHz crystal, fREF = 155.52 MHz, fVCO =

2620.5463 MHz, fOUT = (155.52 × 255/227) MHz, DPLL BW = 50 Hz

Channel 1—DPLL1, APLL1

Channel 0 powered down

RMS Jitter (12 kHz to 20 MHz)

Configuration 1—155.52 MHz

247

Device configuration: fOSC = 52 MHz crystal, fREF = 38.88 MHz, fVCO =

3265.92 MHz, fOUT = 155.52 MHz, DPLL BW = 50 Hz, phase buildout

operation, half divide enabled

Configuration 2—245.76 MHz

280

Device configuration: fOSC = 52 MHz crystal, fREF = 30.72 MHz, fVCO =

3686.4 MHz, fOUT = 245.76 MHz, DPLL BW = 50 Hz, half divide enabled,

internal zero delay operation

Configuration 3—491.52 MHz

323

Device configuration: fOSC = 52 MHz crystal, fCOMP = 19.2 MHz TCXO,

BWCOMP = 50 Hz, fREF = 1 Hz, fVCO = 3932.16 MHz, fOUT = 491.52 MHz, DPLL

BW = 50 mHz, phase buildout operation

Configuration 4—125 MHz

243

Device configuration: fOSC = 52 MHz crystal, fCOMP = 19.2 MHz TCXO,

BWCOMP = 50 Hz, fREF = 125 MHz, fVCO = 3250 MHz, fOUT = 125 MHz, DPLL

BW = 0.1 Hz, phase buildout operation

Configuration 5—312.5 MHz

266

Device configuration: fOSC = 52 MHz crystal, fREF = 25 MHz, fVCO = 3750

MHz, fOUT = 312.5 MHz, DPLL BW = 50 Hz, phase buildout operation

Configuration 6—174.7030837 MHz

264

Device configuration: fOSC = 52 MHz crystal, fREF = 155.52 MHz, fVCO =

3319.3586 MHz, fOUT = (155.52 × 255/227) MHz, DPLL BW = 50 Hz,

phase buildout operation

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