AD9545 datasheet(71/157 Pages) AD

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Data Sheet

AD9545

Rev. A | Page 71 of 157

PROFILE ENABLE

For a DPLL channel to have access to a translation profile, the user

must enable the profile via its corresponding enable Profile x.y

bit (where x is the PLL channel (0 or 1) and y is the profile

number (0 to 5)). The enable Profile x.y bit resides in Bit D0 of

0x1260, Register 0x1280, Register 0x12A0, Register 0x1600,

0x1620, Register 0x1640, Register 0x1660, Register 0x1680, and

corresponding enable Profile x.y bit to Logic 1 (default is Logic 0).

If the translation profile is enabled, the DPLL selects the profile

and the profile becomes active (see the Reference Switching

section for what constitutes an active translation profile).

Certain functional blocks within the AD9545 use the

active/inactive state of a translation profile.

PROFILE PRIORITY

Profile priority works in conjunction with the reference

switching capability of the AD9545 (see the Reference

Switching section). The user programs a priority value via the

5-bit unsigned Profile x.y selection priority bit field (where x is

the PLL channel (0 or 1) and y is the profile number (0 to 5)) in

the register associated with the corresponding translation profile.

The Profile x.y selection priority bit fields reside in Bits[D5:D1]

of Register 0x1200, Register 0x1220, Register 0x1240, Register

0x1260, Register 0x1280, Register 0x12A0, Register 0x1600,

and Register 0x16A0.

When the device must switch from one input reference to

another, it can do so according to user defined priority per the

value stored in the Profile x.y selection priority bit field, where 0

constitutes highest priority and 31 lowest priority.

INPUT REFERENCE SOURCE SELECTION

The AD9545 provides the user with several options for the

reference source that supplies the input clock signal to the

DPLL. These options include any one of the four REFx inputs,

either of the two auxiliary NCOs, and a special configuration

that uses the feedback signal from the other DPLL channel.

Each translation profile can specify a different reference source.

Program the source selection via the 5-bit Profile x.y reference

source selection bit field (where x is the PLL channel (0 or 1)

and y is the profile number (0 to 5)) in the register associated

with the corresponding translation profile. The Profile x.y

reference source selection bit fields reside in Bits[D4:D0] of

0x1621, Register 0x1641, Register 0x1661, Register 0x1681, and

shown in Table 38.

Table 38. Reference Source Selection

Bit Field Value (Decimal)

Source

REFA

REFAA

REFB

REFBB

Feedback from DPLL0 (applies to

Channel 1 only)

Feedback from DPLL1 (applies to

Channel 0 only)

Not applicable

Auxiliary NCO 0

Auxiliary NCO 1

10 to 31

Not applicable

TRANSLATION MODES

Overview

The translation modes govern the way the DPLL responds

when it acquires a reference signal. In general, at the start of a

reference acquisition, the feedback of the DPLL and reference

signals do not have the same phase relationship. As such, when

the DPLL begins an acquisition, it likely exhibits a significant

output disturbance as the loop attempts to compensate for the

phase mismatch. To deal with the output disturbance that

typically results from a reference acquisition, the AD9545 offers

two translation mode types: phase buildout and hitless.

A phase buildout acquisition virtually eliminates the output

disturbance that results from an initial phase mismatch. During

a phase buildout acquisition, the DPLL effectively measures the

initial phase offset between its feedback and reference inputs

and inserts the measured phase offset into the feedback path of

the loop. The measured phase offset is the phase buildout offset.

Insertion of the phase buildout offset into the loop effectively

eliminates the initial phase difference between the feedback and

reference signals, thereby minimizing the disturbance at the

output of the DPLL. The insertion of the phase buildout offset

implies a phase difference between the output of the DPLL and

reference clock signals. This phase difference is the expected

behavior for a phase buildout reference acquisition.

Note that during a phase buildout acquisition, the phase slew

rate limit function does not operate on the buildout phase

transition (see the Phase Slew Rate Limit section of the Digital

PLL (DPLL) section for details on the phase slew rate limiter).

Unlike a phase buildout acquisition, a hitless acquisition

ultimately results in a phase matching of output of the DPLL

and reference clock signals. As such, a hitless translation mode

is a prerequisite for zero delay operation. Given a phase

mismatch between the reference of the DPLL and feedback

signals at the start of an acquisition, the DPLL temporarily

changes its output frequency to steer the phase difference

toward zero. The AD9545 optimizes this process by assessing

the initial phase relationship between the reference and

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