MMPF0100Z datasheet(14/128 Pages) NXP

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NXP Semiconductors

PF0100Z

GENERAL DESCRIPTION

General description

The PF0100Z is the power management integrated circuit (PMIC) designed primarily for use with NXP’s i.MX 6 series of application

processors.

5.1

Features

This section summarizes the PF0100Z features.

• Input voltage range to PMIC: 2.8 V - 4.5 V

• Buck regulators

•

Four to six channel configurable

• SW1A/B/C, 4.5 A (single); 0.3 V to 1.875 V

• SW1A/B, 2.5 A (single/dual); SW1C 2.0 A (independent); 0.3 V to 1.875 V

•SW2, 2.0 A; 0.4 V to 3.3 V (2.5 A; 1.2 V to 3.3 V (22))

• SW3A/B, 2.5 A (single/dual); 0.4 V to 3.3 V

•SW3A, 1.25 A (independent); SW3B, 1.25 A (independent); 0.4 V to 3.3 V

•SW4, 1.0 A; 0.4 V to 3.3 V

• SW4, VTT mode provide DDR termination at 50% of SW3A

•

Dynamic voltage scaling

•

Modes: PWM, PFM, APS

•

Programmable output voltage

•

Programmable current limit

•

Programmable soft start

•

Programmable PWM switching frequency

•

Programmable OCP with fault interrupt

• Boost regulator

•

SWBST, 5.0 V to 5.15 V, 0.6 A, OTG support

•

Modes: PFM and Auto

•

OCP fault interrupt

•LDOs

•

Six user programable LDO

• VGEN1, 0.80 V to 1.55 V, 100 mA

• VGEN2, 0.80 V to 1.55 V, 250 mA

• VGEN3, 1.8 V to 3.3 V, 100 mA

• VGEN4, 1.8 V to 3.3 V, 350 mA

• VGEN5, 1.8 V to 3.3 V, 100 mA

• VGEN6, 1.8 V to 3.3 V, 200 mA

•

Soft start

•

LDO/switch supply

• VSNVS (1.0/1.1/1.2/1.3/1.5/1.8/3.0 V), 400

μA

• DDR memory reference voltage

•VREFDDR, 0.6 V to 0.9 V, 10 mA

•16 MHz internal master clock

• OTP (one time programmable) memory for device configuration

•

User programmable start-up sequence and timing

• Battery backed memory including coin cell charger

•I2C interface

• User programmable standby, sleep, and off modes

Notes

22.

SW2 capable of 2.5 A in NP/F9/FA versions

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