MMPF0100Z datasheet(93/128 Pages) NXP

93 / 128 page

NXP Semiconductors

PF0100Z

FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

6.4.7.1

Coin cell battery backup

The LICELL pin provides for a connection of a coin cell backup battery or a “super” capacitor. If the voltage at VIN goes below the VIN

threshold (VTL1 and VTL0), contact-bounced, or removed, the coin cell maintained logic is powered by the voltage applied to LICELL. The

supply for internal logic and the VSNVS rail switch over to the LICELL pin when VIN goes below VTL1 or VTL0, even in the absence of a

voltage at the LICELL pin, resulting in clearing of memory and turning off VSNVS. Applications concerned about this behavior can tie the

LICELL pin to any system voltage between 1.8 V and 3.0 V. A small capacitor should be placed from LICELL to ground under all

circumstances.

VSNVS AC and transient

tONSNVS

Turn-on time (load capacitor, 0.47

μF)

VIN = UVDET to 90% of VSNVS

VCOIN = 0.0 V, ISNVS = 5.0 μA

VSNVSVOLT[2:0] = 000 to 110

––

(75), (76)

VSNVSOSH

Start-up overshoot

VSNVSVOLT[2:0] = 000 to 110

ISNVS = 5.0 μA

dVIN/dt = 50 mV/μs

–40

VSNVSLITR

Transient line response ISNVS = 75% of ISNVSMAX

3.2 V < VIN < 4.5 V, VSNVSVOLT[2:0] = 110

2.45 V < VIN < 4.5 V, VSNVSVOLT[2:0] = [000] - [101]

–

VSNVSLOTR

Transient load response

VSNVSVOLT[2:0] = 110

3.1 V (UVDETL)< VIN ≤ 4.5 V

ISNVS = 75 to 750 μA

VSNVSVOLT[2:0] = 000 to 101

2.45 V < VIN ≤ 4.5 V

VTL0 > VIN, 1.8 V ≤ VCOIN ≤ 3.3 V

ISNVS = 40 μA to 400 μA

Refer to Figure 25

2.8

–

1.0

–

2.0

VSNVS DC, switch

VINSNVS

Operating input voltage

Valid coin cell range

1.8

–

3.3

ISNVS

Operating load current

5.0

–

400

μA

RDSONSNVS

Internal switch RDS(on)

VCOIN = 2.6 V

–

100

VTL1

VIN threshold (VIN powered to coin cell powered)

VSNVSVOLT[2:0] = 110

2.725

2.90

3.00

(74)

VTH1

VIN threshold (coin cell powered to VIN powered)

VSNVSVOLT[2:0] = 110

2.775

2.95

3.1

Notes

74.

During crossover from VIN to LICELL, the VSNVS output voltage may drop to 2.7 V before going to the LICELL voltage. Though this is outside

the specified DC voltage level for the VDD_SNVS_IN pin of the i.MX 6, this momentary drop does not cause a malfunction. The i.MX 6’s RTC

continues to operate through the transition, and as a worst case may switch to the internal RC oscillator for a few clock cycles before switching

back to the external crystal oscillator.

75.

The start-up of VSNVS is not monotonic. It first rises to 1.0 V and then settles to its programmed value within the specified tr1 time.

76.

From coin cell insertion to VSNVS = 1.0 V, the delay time is typically 400 ms.

77.

For 1.8 V ISNVS limited to 100 μA for VCOIN < 2.1 V

Table 110. VSNVS electrical characteristics (continued)

All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, VSNVS = 3.0 V,

ISNVS = 5.0 μA, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V,

VSNVS = 3.0 V, ISNVS = 5.0 μA, and 25 °C, unless otherwise noted.

Symbol

Parameter

Min

Typ

Max

Unit

Notes

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