MMPF0100Z datasheet(21/128 Pages) NXP

21 / 128 page

NXP Semiconductors

PF0100Z

FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

6.1.2.2

PWRON pin configuration

The PWRON pin can be configured as either a level sensitive input (PWRON_CFG = 0), or as an edge sensitive input (PWRON_CFG = 1).

As a level sensitive input, an active high signal turns on the part and an active low signal turns off the part, or puts it into sleep mode. As

an edge sensitive input, such as when connected to a mechanical switch, a falling edge turns on the part and if the switch is held low for

greater than or equal to 4.0 seconds, the part turns off or enters sleep mode.

6.1.2.3

I2C address configuration

The I2C device address can be programmed from 0x08 to 0x0F. This allows flexibility to change the I2C address to avoid bus conflicts.

Address bit, I2C_SLV_ADDR[3] in OTP_I2C_ADDR register is hard coded to “1” while the lower three LSBs of the I2C address

(I2C_SLV_ADDR[2:0]) are programmable as shown in Table 14.

6.1.2.4

Soft start ramp rate

The start-up ramp rate or soft start ramp rate can be chosen from the same options as shown in 6.4.4.2.1 Dynamic voltage scaling, page

34.

Table 12. Start-up Sequence Clock Speed

SEQ_CLK_SPEED[1:0]

Time (

μs)

500

1000

2000

4000

Table 13. PWRON configuration

PWRON_CFG

Mode

PWRON pin HIGH = ON

PWRON pin LOW = OFF or sleep mode

PWRON pin pulled LOW momentarily = ON

PWRON pin LOW for 4.0 seconds = OFF or sleep mode

Table 14. I2C address configuration

I2C_SLV_ADDR[3]

hard coded

I2C_SLV_ADDR[2:0]

I2C device address

(Hex)

000

0x08

001

0x09

010

0x0A

011

0x0B

100

0x0C

101

0x0D

110

0x0E

111

0x0F

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