MMPF0100Z datasheet(16/128 Pages) NXP

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NXP Semiconductors

PF0100Z

GENERAL DESCRIPTION

5.3.2.1

Interface signals

5.3.2.1.1

PWRON

PWRON is an input signal to the IC generating a turn-on event. It can be configured to detect a level, or an edge using the PWRON_CFG

bit. Refer to section 6.4.2.1 Turn on events, page 30 for more details.

5.3.2.1.2

STANDBY

STANDBY is an input signal to the IC. When it is asserted, the part enters standby mode and when de-asserted, the part exits standby

mode. STANDBY can be configured as active high or active low using the STANDBYINV bit. Refer to the section 6.4.1.3 Standby mode,

page 28 for more details.

Note: When operating the PMIC at VIN ≤ 2.85 V and VSNVS is programmed for a 3.0 V output, a coin cell must be present to provide

VSNVS, or the PMIC does not reliably enter and exit the STANDBY mode.

5.3.2.1.3

RESETBMCU

RESETBMCU is an open-drain, active low output configurable for two modes of operation. In its default mode, it is de-asserted 2.0 ms to

4.0 ms after the last regulator in the start-up sequence is enabled; refer to Figure 6 as an example. In this mode, the signal can be used

to bring the processor out of reset, or as an indicator all supplies have been enabled; it is only asserted for a turn-off event.

When configured for its fault mode, RESETBMCU is de-asserted after the start-up sequence is completed only if no faults occurred during

start-up. At anytime, if a fault occurs and persists for 1.8 ms typically, RESETBMCU is asserted, LOW. The PF0100Z is turned off if the

fault persists for more than 100 ms typically. The PWRON signal restarts the part, though if the fault persists, the sequence described

previously is repeated. To enter the fault mode, set bit OTP_PG_EN of register OTP PWRGD EN to “1”. This register, 0xE8, is located on

Table 136. Extended page 1, page 106 of the register map. To test the fault mode, the bit may be set during TBB prototyping, or the mode

may be permanently chosen by programming OTP fuses.

5.3.2.1.4

SDWNB

SDWNB is an open drain, active low output notifying the processor of an imminent PMIC shut down. It is asserted low for one 32 kHz clock

cycle before powering down and then de-asserted in the OFF state.

5.3.2.1.5

INTB

INTB is an open-drain, active low output. It is asserted when any fault occurs, provided the fault interrupt is unmasked. INTB is de-asserted

after the fault interrupt is cleared by software, which requires writing a “1” to the fault interrupt bit.

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