 |
поискавой системы для электроныых деталей |
|
|
поискавой системы для электроныых деталей |
|
MMPF0100Z датащи(PDF) 97 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
MMPF0100Z датащи(HTML) 97 Page - NXP Semiconductors |
|
|
97 / 128 page  NXP Semiconductors 97 PF0100Z FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS A full description of all interrupt, mask, and sense registers is provided in Tables 116 to 127. SWBSTFAULTI SWBSTFAULTM SWBSTFAULTS SWBST overcurrent limit Sense is 1 if above current limit L to H 8.0 VGEN1FAULTI VGEN1FAULTM VGEN1FAULTS VGEN1 overcurrent limit Sense is 1 if above current limit L to H 8.0 VGEN2FAULTI VGEN2FAULTM VGEN2FAULTS VGEN2 overcurrent limit Sense is 1 if above current limit L to H 8.0 VGEN3FAULTI VGEN3FAULTM VGEN3FAULTS VGEN3 overcurrent limit Sense is 1 if above current limit L to H 8.0 VGEN4FAULTI VGEN4FAULTM VGEN4FAULTS VGEN4 overcurrent limit Sense is 1 if above current limit L to H 8.0 VGEN5FAULTI VGEN5FAULTM VGEN1FAULTS VGEN5 overcurrent limit Sense is 1 if above current limit L to H 8.0 VGEN6FAULTI VGEN6FAULTM VGEN6FAULTS VGEN6 overcurrent limit Sense is 1 if above current limit L to H 8.0 OTP_ECCI OTP_ECCM OTP_ECCS 1 or 2 bit error detected in OTP registers Sense is 1 if error detected L to H 8.0 Notes 79. Debounce timing for the falling edge can be extended with PWRONDBNC[1:0]. Table 116. Register INTSTAT0 - ADDR 0x05 Name Bit # R/W Default Description PWRONI 0 R/W1C 0 Power on interrupt bit LOWVINI 1 R/W1C 0 Low-voltage interrupt bit THERM110I 2 R/W1C 0 110 °C thermal interrupt bit THERM120I 3 R/W1C 0 120 °C thermal interrupt bit THERM125I 4 R/W1C 0 125 °C thermal interrupt bit THERM130I 5 R/W1C 0 130 °C thermal interrupt bit UNUSED 7:6 – 00 unused Table 117. Register INTMASK0 - ADDR 0x06 Name Bit # R/W Default Description PWRONM 0 R/W1C 1 Power on interrupt mask bit LOWVINM 1 R/W1C 1 Low-voltage interrupt mask bit THERM110M 2 R/W1C 1 110 °C thermal interrupt mask bit THERM120M 3 R/W1C 1 120 °C thermal interrupt mask bit THERM125M 4 R/W1C 1 125 °C thermal interrupt mask bit THERM130M 5 R/W1C 1 130 °C thermal interrupt mask bit UNUSED 7:6 – 00 unused Table 115. Interrupt, Mask and Sense Bits (continued) Interrupt Mask Sense Purpose Trigger Debounce time (ms) |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
