MMPF0100Z datasheet(34/128 Pages) NXP

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NXP Semiconductors

PF0100Z

FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

When in standby mode, the regulator outputs the voltage programmed in its standby voltage register and operates in the mode selected

by the SWxMODE[3:0] bits. Upon exiting standby mode, the regulator returns to its normal switching mode and its output voltage

programmed in its voltage register.

Any regulators whose SWxOMODE bit is set to “1” enters sleep mode if a PWRON turn-off event occurs, and any regulator whose

SWxOMODE bit is set to “0” is turned off. In sleep mode, the regulator outputs the voltage programmed in its off (sleep) voltage register

and operates in the PFM mode. The regulator exits the sleep mode when a turn-on event occurs. Any regulator whose SWxOMODE bit

is set to “1” remains on and changes to its normal configuration settings when exiting the sleep state to the on state. Any regulator whose

SWxOMODE bit is set to “0” powers up with the same delay in the start-up sequence as when powering on from off. At this point, the

regulator returns to its default ON state output voltage and switch mode settings.

Table 24 shows the control bits in sleep mode. When sleep mode is activated by the SWxOMODE bit, the regulator uses the set point as

programmed by SW1xOFF[5:0] for SW1A/B/C and by SWxOFF[6:0] for SW2, SW3A/B, and SW4.

6.4.4.2.1

Dynamic voltage scaling

To reduce overall power consumption, processor core voltages can be varied depending on the mode or activity level of the processor.

1. Normal operation: The output voltage is selected by I2C bits SW1x[5:0] for SW1A/B/C and SWx[6:0] for SW2, SW3A/B, and SW4.

A voltage transition initiated by I2C is governed by the DVS stepping rates shown in Table 33 and Table 34.

2. Standby mode: The output voltage can be higher, or lower than in normal operation, but is typically selected to be the lowest state

retention voltage of a given processor; it is selected by I2C bits SW1xSTBY[5:0] for SW1A/B/C and by bits SWxSTBY[6:0] for SW2,

SW3A/B, and SW4. Voltage transitions initiated by a standby event are governed by the SW1xDVSSPEED[1:0] and

SWxDVSSPEED[1:0] I2C bits shown in Table 33 and Table 34, respectively.

3. Sleep mode: The output voltage can be higher or lower than in normal operation, but is typically selected to be the lowest state

retention voltage of a given processor; it is selected by I2C bits SW1xOFF[5:0] for SW1A/B/C and by bits SWxOFF[6:0] for SW2,

SW3A/B, and SW4. Voltage transitions initiated by a turn-off event are governed by the SW1xDVSSPEED[1:0] and

SWxDVSSPEED[1:0] I2C bits shown in Table 33 and Table 34, respectively.

Table 31, Table 32, Table 33, and Table 34 summarize the set point control and DVS time stepping applied to all regulators.

Table 31. DVS control logic for SW1A/B/C

STANDBY

Set point selected by

SW1x[5:0]

SW1xSTBY[5:0]

Table 32. DVS control logic for SW2, SW3A/B, and SW4

STANDBY

Set point selected by

SWx[6:0]

SWxSTBY[6:0]

Table 33. DVS speed selection for SW1A/B/C

SW1xDVSSPEED[1:0]

Function

25 mV step each 2.0

μs

01 (default)

25 mV step each 4.0

μs

25 mV step each 8.0

μs

25 mV step each 16

μs

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