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MMPF0100Z датащи(PDF) 73 Page - NXP Semiconductors

номер детали MMPF0100Z
подробное описание детали  14 channel configurable power management integrated circuit
PDF  128 Pages
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производитель  NXP [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo NXP - NXP Semiconductors

MMPF0100Z датащи(HTML) 73 Page - NXP Semiconductors

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NXP Semiconductors
73
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Figure 23. Boost Regulator Architecture
6.4.5.1
SWBST setup and control
Boost regulator control is done through a single register SWBSTCTL described in Table 87. SWBST is included in the power-up sequence
if its OTP power-up timing bits, SWBST_SEQ[4:0], are not all zeros.
Table 87. Register SWBSTCTL - ADDR 0x66
Name
Bit #
R/W
Default
Description
SWBST1VOLT
1:0
R/W
0x00
Set the output voltage for SWBST
00 = 5.000 V
01 = 5.050 V
10 = 5.100 V
11 = 5.150 V
SWBST1MODE
3:2
R
0x02
Set the switching mode on normal operation
00 = OFF
01 = PFM
10 = Auto (Default)(58)
11 = APS
UNUSED
4
–
0x00
unused
SWBST1STBYMODE
6:5
R/W
0x02
Set the switching mode on standby
00 = OFF
01 = PFM
10 = Auto (Default)(58)
11 = APS
UNUSED
7
–
0x00
unused
Notes
58.
In auto mode, the controller automatically switches between PFM and APS modes depending on the load current.
The SWBST regulator starts up by default in the auto mode, if SWBST is part of the startup sequence.
SWBSTLX
VOBST
Driver
Controller
EA
Z1
Z2
Internal
Compensation
I2C
Interface
SWBSTMODE
VREFUV
VREF
EP
VIN
LBST
CINBST
DBST
SWBSTFB
RSENSE
SC
VREFSC
SWBSTFAULT
OC
UV
COSWBST
SWBSTIN



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