MMPF0100Z datasheet(28/128 Pages) NXP

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NXP Semiconductors

PF0100Z

FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

6.4.1.3

Standby mode

• Depending on STANDBY pin configuration, standby is entered when the STANDBY pin is asserted. This is typically used for low-

power mode of operation.

• When STANDBY is de-asserted, standby mode is exited.

A product may be designed to go into a low-power mode after periods of inactivity. The STANDBY pin is provided for board level control

of going in and out of such deep sleep modes (DSM).

When a product is in DSM, it may be able to reduce the overall platform current by lowering the regulator output voltage, changing the

operating mode of the regulators, or disabling some regulators. The configuration of the regulators in standby is pre-programmed through

the I2C interface.

Note that the STANDBY pin is programmable for active high or active low polarity, and decoding of a Standby event takes into account

the programmed input polarity, as shown in Table 22. When the PF0100Z is powered up first, regulator settings for the standby mode are

mirrored from the regulator settings for the on mode. To change the STANDBY pin polarity to active low, set the STANDBYINV bit via

software first, and then change the regulator settings for standby mode as required. For simplicity, STANDBY is generally referred to as

active high throughout this document.

Since STANDBY pin activity is driven asynchronously to the system, a finite time is required for the internal logic to qualify and respond

to the pin level changes. A programmable delay is provided to hold off the system response to a Standby event. This allows the processor

and peripherals some time after a standby instruction was received to terminate processes to facilitate seamless entering into standby

mode.

When enabled (STBYDLY = 01, 10, or 11) per Table 23, STBYDLY delays the standby initiated response for the entire IC, until the

STBYDLY counter expires. An allowance should be made for three additional 32 k cycles required to synchronize the standby event.

6.4.1.4

Sleep mode

• Depending on the PWRON pin configuration, sleep mode is entered when PWRON is de-asserted and SWxOMODE bit is set.

• To exit sleep mode, assert the PWRON pin.

In the sleep mode, the regulator uses the set point as programmed by SW1xOFF[5:0] for SW1A/B/C and by SWxOFF[6:0] for SW2, SW3A/

B, and SW4. The activated regulators maintain settings for this mode and voltage until the next turn-on event. Table 24 shows the control

bits in sleep mode. During sleep mode, interrupts are active and the INTB pin reports any unmasked fault event.

Table 22. Standby pin and polarity control

STANDBY (pin)(34)

STANDBYINV (I2C bit)(35)

STANDBY control (33)

Notes

33.

STANDBY = 0: System is not in standby, STANDBY = 1: System is in standby

34.

The state of the STANDBY pin only has influence in on mode.

35.

Bit 6 in power control register (ADDR - 0x1B)

Table 23. STANDBY delay - initiated response

STBYDLY[1:0](36)

Function

No delay

One 32 k period (default)

Two 32 k periods

Three 32 k periods

Notes

36.

Bits [5:4] in Power Control Register (ADDR - 0x1B)

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