MMPF0100Z datasheet(4/128 Pages) NXP

4 / 128 page

NXP Semiconductors

PF0100Z

ORDERABLE PARTS

Orderable parts

The PF0100Z is available with both pre-programmed and non-programmed OTP memory configurations. The non-programmed device

uses “NP” as the programming code. The pre-programmed devices are identified using the program codes from Table 1, which also list

the associated NXP reference designs where applicable. Details of the OTP programming for each device can be found in Table 9.

1.1

PF0100Z version differences

PF0100AZ is an improved version of the PF0100Z power management IC. Table 2 summarizes the difference between the two versions

and should be referred to when migrating from the PF0100Z to the PF0100AZ.

Table 1. Orderable part variations

Part Number

Temperature (TA)

Package

Programming

Reference designs

Notes

MMPF0100NPAZES

-40 °C to 105 °C

56 QFN ES, 8x8 mm

0.5 mm pitch WF-Type

(wettable flank)

MCIMX6QAICPU1

MCIMX6SAICPU1

MCIMX6DLAICPU1

(1), (2), (3)

MMPF0100F0AZES

MCIMX6Q-SDP

MCIMX6Q-SDB

MCIMX6DL-SDP

(1), (2)

MMPF0100F6AZES

MMPF0100F8AZES

MMPF0100F9AZES

MCIMX6QPlusAICPU3

(1), (2), (3)

MMPF0100FAAZES

Notes

For tape and reel add an R2 suffix to the part number.

These reference designs use the default startup configuration (VDDOTP = VCOREDIG), which is available on any OTP programmed part.

SW2 can support an output current rating of 2.5 A in NP, F9 and FA versions when SW2ILIM=0

Table 2. Differences between PF0100Z and PF0100AZ

Description

PF0100Z

PF0100AZ

Version identification

Reading SILICON REV register at address 0x03 will

return 0x11. DEVICEID register at address 0x00 will

read 0x10 in PF0100Z and PF0100AZ

Reading SILICON REV register at address 0x03 will

return 0x21. DEVICEID register at address 0x00 will

read 0x10 in PF0100Z and PF0100AZ

VSNVS current limit

VSNVS current limit increased in the PF0100AZ. see VSNVS LDO/switch

OTP_FUSE_PORx register setting during OTP

programming

In the PF0100Z, FUSE_POR1, FUSE_POR2, and

FUSE_POR3 bits are XOR’ed into the

FUSE_POR_XOR bit. The FUSE_POR_XOR bit

has to be 1 for fuses to be loaded during startup.

This can be achieved by setting any one or all of the

FUSE_PORx bits during OTP programming.

In the PF0100AZ, the XOR function is removed. It is

required to set FUSE_POR1, FUSE_POR2, and

FUSE_POR3 bits during OTP programming.

Erratum ER19

Erratum ER19 applicable to PF0100Z. Applications

expecting to operate in the conditions mentioned in

ER19 need to implement an external workaround to

overcome the problem. Refer to the product errata

for details

Errata ER19 fixed in PF0100AZ. External

workaround not required

Erratum ER20

Erratum ER20 applicable to PF0100Z

Errata ER20 fixed in PF0100AZ

Erratum ER22

Erratum ER22 applicable to PF0100Z

Errata ER22 fixed in PF0100AZ. Workaround not

required

Ambient operating temperature

-40 °C to 85 °C

-40 °C to 105 °C

MMPF0100Z датащи(PDF) 4 Page - NXP Semiconductors

MMPF0100Z датащи(HTML) 4 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL