PC87413 datasheet(117/257 Pages) NSC

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6.0

ACCESS.bus Interface

This section is relevant only for the PC87413 and PC87417. In the PC87414 and PC87416, all ACCESS.bus Interface

bits and signals that influence other modules are at their default value.

The ACCESS.bus Interface is a two-wire synchronous serial interface compatible with the ACCESS.bus (Specification Rev.

3.0 Sep. 1995) and with Intel's SMBus (Speciﬁcation Rev 1.1 Dec. 11, 1998). The ACCESS.bus Interface acts as a slave

device controlled by a bus master. The ACCESS.bus Interface uses proprietary commands for AdvancedI/O access, com-

patible with the Physical, Data Link and Transport layers defined by the above specifications.

This chapter describes the ACCESS.bus Interface functional block.

6.1

OVERVIEW

The ACCESS.bus protocol uses a two-wire interface for bidirectional communication between the devices connected to the

bus. The two interface lines are the Serial Data Line (ACBDAT) and the Serial Clock Line (ACBCLK). These open-drain lines

must be connected to a positive supply via an internal or an external pull-up resistor and remain high when the bus is idle.

Each device connected to the bus has a unique address and can operate as a transmitter or a receiver (though some pe-

ripherals are only receivers).

During data transactions, the master device initiates the transaction with an attached peripheral, generates the clock signal

and terminates the transaction. When the master sends a slave address or data, the peripheral behaves as a receiver. When

the slave responds and sends data to the master, the peripheral behaves as a transmitter.

6.2

FUNCTIONAL DESCRIPTION

6.2.1

Bus Signals

ACBDAT and ACBCLK Signals

The ACBDAT and ACBCLK are open-drain signals. The device permits the user to define whether to enable or disable the

internal pull-up of these two signals (at reset, the internal pull-up is disabled).

Clock Frequency

The PC8741x device is a slave device that synchronizes to the clock frequency of the ACCESS.bus clock. The maximum

clock frequency is 100 kHz and the minimum is 10 kHz (limited by the 50

µsec maximum high time required by the standards

to detect a Bus Idle condition). However, since the PC8741x device is a slave device, the minimum clock frequency limitation

is ignored. The clock low period may be extended by stall periods initiated by the ACCESS.bus Interface (see Section 11.5.6

on page 246).

6.2.2

Data Transactions

One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock (ACBCLK). Con-

sequently, throughout the high period of the clock, the data must remain stable (see Figure 30). Any change in mid-

transaction on the ACBDAT line during the high period of the ACBCLK aborts the transaction and releases the ACBDAT

signal (to high level), thus generating Negative Acknowledge (NACK) cycles (see Section 6.2.4 on page 118). In addition,

the PC8741x device sets the BUSERR bit in the ACBCST register (see Section 6.3.2 on page 127). Data must be driven

onto the bus only during the low ACBCLK period. This protocol permits a single data line to transfer both command/control

information and data, using the synchronous serial clock.

During each clock cycle, while the slave handles the received data or prepares the data to be sent, it can stall the master.

The slave can do this for each bit transferred or on a byte boundary by holding ACBCLK low to extend the clock-low period.

Typically, slaves extend the first clock cycle of a transfer if a byte written has not yet been stored or if the byte to be read is

not yet ready. Some microcontroller-based masters with limited hardware support for ACCESS.bus extend the access after

each bit, thus allowing the software to handle the bit.

Each data transaction is composed of a Start Condition, a number of byte transfers (defined by the protocol) and a Stop

Condition to terminate the transaction. Each byte (eight bits) is transferred with the most significant bit first. After each byte,

an Acknowledge signal must follow. The following sections provide further details of this process.

ACBDAT

ACBCLK

Data Line Stable:

Data Valid

Figure 30. Data Bit Transfer

Change of Data

Allowed

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