PC87413 datasheet(113/257 Pages) NSC

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5.0 X-Bus Extension (Continued)

Revision 1.2

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5.4.10

X-Bus Select Mode Register (XZM0 to XZM3)

These registers control the operation mode of chip select XCSn, where n is from 0 to 3.

Power Well:VSB

Location:Offset 0Fh (XZM0)

Location:Offset 10h (XZM1)

Location:Offset 11h (XZM2)

Location:Offset 12h (XZM3)

Type:

Varies per bit

Bit

76543210

Name

LOCKXSCF

WRSTAT

SMIWREN

XCSPOL

XCSTIM

TRANSMD

TRANSPD

Reset

00000000

Bit

Type

Description

R/W1S

LOCKXSCF (X-Bus Select Configuration Lock). Locks the conﬁguration registers of the respective

XCSn signal (both XZCNFn register and XZMn register) by disabling writing to all their bits (including to

itself). An exception to this is the WRSTAT bit of the XZMn register. In addition, it locks the bits in the

XBCNF register. Once set, this bit can be cleared either by the VDD Power-Up reset (or Hardware

reset) or by the VSB Power-Up reset, according to the VSBLOCK bit in the ACBLKCTL register (see

Section 6.3.4 on page 128). In addition, this bit is cleared by setting the UNLOCKX bit in the

ACBLKCTL register (PC87417).

0: Lock Disabled (default)

1: Lock Enabled, protecting the configuration for this chip select

R/W1C

WRSTAT (Write Status). This bit is set if a write to the chip select occurred. Writing 1 to this bit clears

it to 0. WRSTAT is not locked by the LOCKXSCK bit.

0: No write detected (default)

1: Write to the chip select detected

R/W or

SMIWREN (SMI-on-Write Enable). Enables the generation of an SMI, if the WRSTAT bit is set by the

occurrence of a write to the chip select.

0: SMI Disabled (default)

1: SMI Enabled

R/W or

XCSPOL (XCS Polarity Control). Selects the polarity of the XCSn signal.

0: Active low - idle = 1, select = 0 (default)

1: Active high - idle = 0, select = 1

3-2

R/W or

XCSTIM (XCS Timing Control). Selects the timing of the XCSn signal during read and write

transactions in mode 0. If TRANSMD bit is set to mode 1, the value of these bits is ignored and they

are treated as ‘00’.

Bits

3 2

Function

0 0: Normal XCSn timing for both read and write cycles (default)

0 1: Normal XCSn timing during write cycles; XRD_XEN timing for XCSn during read cycles

1 0: Normal XCSn timing during read cycles; XWR_XRW timing for XCSn during write cycles

11: XRD_XEN timing for XCSn during read cycles; XWR_XRW timing for XCSn during write cycles

R/W or

TRANSMD (X-Bus Transaction Mode). Selects the X-Bus transaction mode pertaining to the behavior

of the XWR_XRW and XRD_XEN signals during a transaction.

0: Mode 0 - This is an ISA-like mode. When accessing the XCSn, XWR_XRW functions as an active low

write signal and XRD_XEN functions as an active low read signal (default)

1: Mode 1 - In this mode, when accessing the XCSn, XWR_XRW functions as a read/write signal (high

for a read transaction and low for a write transaction) and XRD_XEN functions as an active high enable

signal

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